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Education, IEEE Transactions on

Issue 4 • Date Nov 1994

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Displaying Results 1 - 8 of 8
  • On the derivation of stored electrostatic energy from a collection of discrete point charges

    Publication Year: 1994 , Page(s): 332 - 333
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (108 KB)  

    This correspondence presents a different perspective on the energy required to position a collection of arbitrary discrete point charges in a space with no externally provided electric field. By examining all permutations of the charge placements, a clear derivation of the familiar result is given, without relying on knowledge of reciprocity View full abstract»

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  • Verifying SPICE results with hand calculations: handling common discrepancies

    Publication Year: 1994 , Page(s): 358 - 368
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (996 KB)  

    Students enrolled in a capstone design course on analog integrated circuits often encounter calculational difficulties when they attempt to verify key circuit parameters predicted by computer simulations using SPICE. Discrepancies between their hand calculations and SPICE values sometimes exceed 200%. This paper reviews some commonly encountered discrepancies, describes major causes of significant errors, and offers solutions that have been found to be effective. In particular, this paper discusses the impacts of variable transistor current gains (β ac and βdc) on AC gain, input impedance, and quiescent point (Q point) determination. Since realistic computer simulations depend on realistic numerical models of active devices, SPICE parameters that realistically model BJTs, JFETs, and MOSFETs are given. The paper also discusses the large discrepancies typically found when calculating the output resistance (Rout) of a Class AB push-pull stage operating near 0 VDC, the common mode rejection ratio (CMRR) of an actively loaded differential stage, and the frequency response of an internally compensated op amp circuit. Lastly, suggestions and recommendations for avoiding many calculational pitfalls also are presented View full abstract»

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  • A discrete phase-locked loop for undergraduate laboratories

    Publication Year: 1994 , Page(s): 372 - 374
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    Phase-locked loop (PLL) experiments in undergraduate instructional laboratories are usually designed around a monolithic IC chip. However, insight into circuit operation is mostly lost with use of the IC chip. In this paper, a PLL circuit consisting of only three transistors is presented. Given its simple topology, it can be realized with discrete components and requires minimal analysis. Hence, the presented circuit is ideally suited for demonstrating PLL principles in undergraduate laboratories View full abstract»

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  • An advanced IC processing laboratory at the University of Notre Dame

    Publication Year: 1994 , Page(s): 334 - 340
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    A new integrated circuits fabrication laboratory course was developed at the University of Notre Dame, USA. The course was taught first to graduate students, who helped to develop the processes, and then to seniors. Complementary metal oxide semiconductor (CMOS) test circuits of up to 150 transistors per circuit, with 5-micron minimum geometries on 4-inch wafers were successfully fabricated. In this paper, the authors discuss the construction, funding, and operation of the facility in which the course is taught. They also discuss the fabrication process used by the students, class assignments, and results of the first semester in which the course was offered to seniors View full abstract»

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  • The well tempered coil winder

    Publication Year: 1994 , Page(s): 329 - 331
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    Inductance is a central concept in the basic education of electrical and electronic engineering, yet the practical problem of making inductors with prescribed values is rarely taught. This paper discusses the design of air-cored inductors having the economical Brooks inductor geometry. It introduces a manufacturing method based on scaling rules that can be readily implemented in the teaching environment View full abstract»

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  • The two-pole two-zero root locus

    Publication Year: 1994 , Page(s): 369 - 371
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    The author highlights the unity negative feedback root locus of a loop gain having two real poles lying along the real axis to the right of two real zeros. He demonstrates that the complex portion of the root locus (of the closed-loop negative feedback system) is a circle. He locates the center and computes the radius of the circle, and illuminates the stability of the closed-loop system View full abstract»

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  • Course development in IC manufacturing

    Publication Year: 1994 , Page(s): 341 - 350
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (884 KB)  

    A traditional curriculum in electrical engineering separates semiconductor processing courses from courses in circuit design. As a result, manufacturing topics involving yield management and the study of random process variations impacting circuit behaviour are usually vaguely treated. The subject matter of this paper is to report a course developed at Texas A&M University, USA, to compensate for the aforementioned shortcoming. This course attempts to link technological process and circuit design domains by emphasizing aspects such as process disturbance modeling, yield modeling, and defect-induced fault modeling. In a rapidly changing environment where high-end technologies are evolving towards submicron features and towards high transistor integration, these aspects are key factors to design for manufacturability. The paper presents the course's syllabus, a description of its main topics, and results on selected project assignments carried out during a normal academic semester View full abstract»

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  • Integrated circuit teaching through top-down design

    Publication Year: 1994 , Page(s): 351 - 357
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    This paper describes the organization, development, and results of an integrated circuit design course where the bottom-up teaching approach adopted in textbooks has been managed in conjunction with the top-down strategy of modern design methodologies. The deliverables and milestones established for the teaching, learning, and design activities have been successfully met up to the level of obtaining simulation results demonstrating the functional and/or electrical performance of a number of application specific integrated circuits for communication systems which not only exhibit some innovative solutions but also demonstrate potential practical applicability in industry View full abstract»

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Aims & Scope

Educational research, methods, materials, programs, and technology in electrical engineering, computer engineering, and fields within the scope of interest of IEEE.

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Meet Our Editors

Editor-in-Chief
Jeffrey E. Froyd
Texas A&M University