2016 International Conference on Integrated Circuits and Microsystems (ICICM)

23-25 Nov. 2016

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Displaying Results 1 - 25 of 83
  • [Front cover]

    Publication Year: 2016, Page(s): 1
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  • [Title page]

    Publication Year: 2016, Page(s): 1
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  • Preface

    Publication Year: 2016, Page(s): ix
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  • [Copyright notice]

    Publication Year: 2016, Page(s): 1
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  • Author index

    Publication Year: 2016, Page(s):381 - 383
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  • Table of contents

    Publication Year: 2016, Page(s):iii - viii
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  • System level power consumption modeling and optimization for coarse-grained reconfigurable architectures

    Publication Year: 2016, Page(s):1 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (353 KB) | HTML iconHTML

    Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform because of its high performance and low cost. With the popularization of CGRAs, low power design has become one of the most challenging tasks to concern. This paper presents an improved instruction level power estimation model at the system-level as a platform for power optimization. With this model, we adopt a modified res... View full abstract»

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  • Design and implementation of AGC algorithm circuit for high PAPR signal

    Publication Year: 2016, Page(s):7 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (390 KB) | HTML iconHTML

    This paper presents an automatic gain control (AGC) algorithm and circuit used in wireless communication receivers with high peak power to average power ratio (PAPR) signal. Combining fixed gain amplifier and programmable attenuator, the AGC function can be implemented by comparing the strength of thresholds with reading two points power detection value of radio frequency (RF) signal. The proposed... View full abstract»

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  • Internal matching circuit design of RF LDMOS power transistor

    Publication Year: 2016, Page(s):11 - 14
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (442 KB) | HTML iconHTML

    This paper reports an optimized design of internal matching circuit for RF LDMOS power transistors. Efforts are mainly focused on the implementation of output internal matching circuit design, where a Shunt-L network structure is adopted. Computer-aided design (CAD) tools are employed to help rearrange the layout of bonding wire arrays to achieve a more uniform current distribution. Consequently, ... View full abstract»

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  • A programmable power ground network optimization flow aiming at IR-drop reduction

    Publication Year: 2016, Page(s):15 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (359 KB) | HTML iconHTML

    The maximum operation frequency of integrated circuits (ICs) has reached multiple Giga Hertz. When a large number of transistors switch at the same time, high current consumption is generated. The parasitic resistance of the power ground network (PGN) combining with the high current consumption, generate significant IR-drop. This paper presents a novel PGN optimization flow, which can monitor the ... View full abstract»

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  • Adaptive run-length encoding circuit based on cascaded structure for target region data extraction of remote sensing image

    Publication Year: 2016, Page(s):20 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (873 KB)

    In order to reduce the pressure of data storage and transmission on satellite, researchers implemented a method of object region data extraction from remote sensing image in orbit. This method stores and downloads pixels of interesting region through interesting region labeling. But encoding data volume (EDV), hardware scale and real-time property (RTP) are difficult to be balanced. To solve this ... View full abstract»

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  • A fault simulation method based on mutated truth table of logic gates

    Publication Year: 2016, Page(s):28 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (246 KB) | HTML iconHTML

    A new fault modeling and simulation method based on VLSI is proposed to evaluate the fault coverage in VLSI accurately. Firstly, inject the circuit-level faults into the logic gates by means of simulation and experiments. Built the fault dictionary consisted of MTTs by analyzing the experimental effect of faults on function. Secondly, considering the MTTs and their weights, a testing coverage mode... View full abstract»

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  • Theoretical analysis of buffer trapping effects on off-state breakdown between gate and drain in AlGaN/GaN HEMTs

    Publication Year: 2016, Page(s):33 - 36
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (326 KB) | HTML iconHTML

    In this paper, AlGaN/GaN HEMTs with different device dimensions were designed and fabricated to investigate the relationship between off-state breakdown voltage and gate-to-drain spacing. It is found that the off-state breakdown voltage increases almost linearly with gate-to-drain spacing with the slop of about 46.8V/gm. Sentaurus software was used to find the physical mechanism of this phenomenon... View full abstract»

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  • Design of signal conditioning circuit based on MEMS acceleration sensor

    Publication Year: 2016, Page(s):37 - 40
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB) | HTML iconHTML

    The MEMS acceleration sensors have been widely applied in many fields, especially in the detection of geological and geological imaging. In this paper, on the basis of MEMS sensors designed the sensor peripheral circuit and the signal conditioning circuit. The theoretical simulation and experimental test are adopted to carry out the shallow geological exploration project. Experimental results show... View full abstract»

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  • Irradiation side-channel attack on cryptographic chip

    Publication Year: 2016, Page(s):41 - 45
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB) | HTML iconHTML

    Irradiation Side-Channel Attack (ISCA) is an innovation for cracking cryptosystem and circuit structure without physical damage. Based on the ISCA architecture design, we proposed an irradiation centric side-channel attack model to induce the cryptographic chip to generate soft error, and we build an irradiation soft error model to present the circuit's behavior. We design a formal verification vi... View full abstract»

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  • An automatic test equipment for integrated circuits in the extreme environments

    Publication Year: 2016, Page(s):46 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (714 KB) | HTML iconHTML

    This paper describes an automatic test equipment for integrated circuits. Most traditional automatic test equipments focus on integrated circuits tests in conventional environments. They usually can not test integrated circuits in the extreme environments, such as thermal cycling, thermal vacuum, vibration and shock. Some can accomplish the tests in only one kind of extreme environment. We invent ... View full abstract»

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  • Web-based power board using raspberry Pi

    Publication Year: 2016, Page(s):50 - 54
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    Considered as one of the major catastrophes, fire caused by unattended outlets that may spread quickly to neighboring building structures can inflict substantial losses. Converging wireless and mobile technology, a new device is designed to be used for monitoring and controlling the custom-built power board that can prevent accidents from happening, mitigating their consequences and increasing pub... View full abstract»

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  • Stochastic-based logic circuit synthesis and implementation through large-fanin threshold logic with magnetic tunneling junctions

    Publication Year: 2016, Page(s):55 - 60
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (491 KB) | HTML iconHTML

    The logic design framework based on Threshold Logic Gate (TLG), combined with emerging spintronic device technology, can achieve ultra-high-performance computing circuits. However, large-fanin threshold logic gates with emerging devices often lead to reduced variation tolerance for memristance, therefore resulting in a so-called fan-in restriction problem. This limitation prevents both large thres... View full abstract»

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  • Timing performance for MRF-based circuits with low supply voltage

    Publication Year: 2016, Page(s):61 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB) | HTML iconHTML

    Markov Random Field (MRF) based design methodology presents a new approach to establish high noise-immune structure for ultra-low power circuit designs. The MRF design technique is able to significantly improve the reliability and interference tolerance of the logic circuits. The main idea of this methodology is that the circuit has the highest likelihood for correct logic states from the viewpoin... View full abstract»

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  • Band calibration of joint dual VCOs covering wide frequency range

    Publication Year: 2016, Page(s):65 - 69
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    A band calibration algorithm for wide frequency coverage dual VCOs (Voltage-Controlled Oscillator) is presented. A high frequency (9.5 GHz~12.5GHz) and a low frequency (6 GHz~9.5GHz) VCO are integrated in PLL circuit for high-speed serial data transmission applications. Algorithm details are presented with calibration precision and time expenditure discussed. This algorithm has been successfully i... View full abstract»

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  • Researches of UWB MMIC control circuits and LTCC 3D integrated circuit technology

    Publication Year: 2016, Page(s):70 - 80
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    This paper introduces the research results of the GaAs ultra-wideband MMIC control circuit technology, including: ultra-wideband digital phase shifter, digital attenuator, absorption type switch, reflective switch and vector modulator. The research results of three-dimensional integrated circuit technology based on LTCC are also proposed in this paper, including a variety of LTCC bandpass filters,... View full abstract»

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  • A sub-1-ppm/°C curvature-compensated bandgap voltage reference

    Publication Year: 2016, Page(s):81 - 85
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB) | HTML iconHTML

    A new sub-1-ppm/°C curvature-compensated bandgap voltage reference (BGR) is presented in this paper. The Complementary to Absolute Temperature (CTAT) voltage component of a forward biased BJT is first well balanced with a Proportional to Absolute Temperature (PTAT) voltage, leaving only a high order logarithmic error with the form of TlnT. This residual non-linear error is corrected by a di... View full abstract»

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  • Evaluation index system for embryonic self-healing strategy

    Publication Year: 2016, Page(s):86 - 90
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB) | HTML iconHTML

    In the digital circuit, especially in the study of very large scale integrated circuit system, the system fault-repair has been the key and difficult point for scientists trying to solve, the emergence of the bionic hardware has opened up a new train of thought to solve this problem. Researchers put forward a series of bionic hardware structures and self-healing methods, but there is short of a un... View full abstract»

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  • An improved ternary three-rail JK flip-flop design

    Publication Year: 2016, Page(s):91 - 94
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2753 KB) | HTML iconHTML

    On the issue of the special structure of multiple-valued trigger with multiple-rail-output, a synchronous edge-triggered improved ternary JK flip-flop with three-rail output structure is presented based on the negative differential resistance (NDR) characteristic and the literal operation as well as the module operation. The ternary NDR JK flip-flop could set the logic values of the output to real... View full abstract»

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  • Design and implementation of Ku-band frequency synthesizer

    Publication Year: 2016, Page(s):95 - 98
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    The design scheme and implementation of a PLL stepped-frequency source is herein introduced. The PLL's phase noise is first discussed. Combined with basic principles and operating characteristic of HMC703, a design is next given in Ku-band, which utilizes the external VCO chip to form the PLL. Parameters of the loop filter and the phase noise simulations are provided by HITTITE PLL Design. Through... View full abstract»

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