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Circuits, Devices and Systems, IEE Proceedings -

Issue 5 • Date Oct 1994

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Displaying Results 1 - 15 of 15
  • New global routing subsystem for CMOS gate arrays

    Publication Year: 1994 , Page(s): 421 - 426
    Cited by:  Papers (20)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    A new global routing subsystem, the `LSIS-II Layout System' for CMOS gate array, is presented. This subsystem consists of three new algorithms, the main purpose of which is to assign available resources evenly. The first two algorithms, called EOFCW and EOFCC, show how to arrange nets so that horizontal resources are used evenly; the third algorithm PACR helps the channel router to utilise vertical resources in the channel reasonably by reassigning some pins in the contact region and thereby eliminate the bottle-necks of the horizontal resources. The present algorithm is different from those existing because it adjusts nets by analysing usable resources and the features of nets. Moreover, using the soft interface concept of system design, this subsystem considers not only the characteristics of the placement and initial global routing but also the requirement of a detailed routing for resources. The subsystem has been implemented on Micro VAX-II. Experimental results verify that the subsystem is quite efficient View full abstract»

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  • Parametric yield optimisation of MOS VLSI circuits based on simulated annealing and its parallel implementation

    Publication Year: 1994 , Page(s): 387 - 398
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (796 KB)  

    As device dimensions continuously scale down in current MOS VLSI technology, statistical tolerances of process parameters become more significant. Thus, for circuit designers, it is essential to estimate the influence of such variations on circuit performances and to optimise the circuit so that the maximum yield is obtained. This paper presents an approach for parametric yield optimisation of MOS VLSI circuits, in which both the simulated annealing and gradient algorithms are combined to improve the computational efficiency. With respect to other methods the proposed approach can be considered more general and robust. In addition, it is able to take deterministic parameters into account and to solve multiobjective problems. To improve the computational efficiency, the method has been implemented in a parallel computing machine based on an array of 16 transputers. Several examples of digital-and analog circuit design optimisation are reported to demonstrate the validity of the approach View full abstract»

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  • Distributed arithmetic perceptron

    Publication Year: 1994 , Page(s): 382 - 386
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    The shift of the nonlinearity from the neuron to the input allows the realisation of any mapping by a single perceptron. The resulting perceptron is unimodal and consequently there are no problems of local minima and excessive time-consuming training procedures. In the paper a method is proposed for carrying out this preprocessing in a more general way. Moreover, it is shown that the weights of the connections can be explicitly determined from the training set View full abstract»

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  • Performance characterisation of a microwave transistor

    Publication Year: 1994 , Page(s): 337 - 344
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    The maximum transducer power gain GTmax of a bilateral microwave transistor-is analytically expressed in terms of only noise figure F, input-VSWR Vi and the open-circuit parameters |z|. The analysis is based on a geometrical approach using the constant noise, input VSWR and gain circles in the source and input impedance planes keeping the solution within the physical bounds. The corresponding source Zs and load ZL terminations are also obtained analytically. Cross-relations among the possible (F, V i, GTmax) triplets have been utilised in obtaining the performance contours of a microwave transistor at an operating frequency and bias condition. This type of representation of performance promises to be used in data sheets of microwave transistors by manufacturers in forthcoming years View full abstract»

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  • Optimisation efficiency in behavioural synthesis

    Publication Year: 1994 , Page(s): 399 - 406
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    Behavioural synthesis is the process whereby the mapping of system operation (behaviour) onto a physical circuit is essentially automated. In general, there are many ways in which a given design can be realised and each alternative design will have different physical parameters (area, speed and power dissipation being the most common). One of the key features of a good silicon compiler is that it allows the user to explore the `design space' corresponding to the behavioural description; this means that the system must be capable of producing alternative (but behaviourally equivalent) designs relatively quickly. This paper describes the optimisation technique used in the MOODS (multiple objective optimisation behavioural synthesis) system and looks at the efficiency of the various subprocesses. The conclusions are that even for a large synthesis task, the time taken taken for MOODS to generate alternative designs is sufficiently low that the user response (in evaluating alternative designs) is essentially the rate limiting step in the overall design process. Typically, MOODS can generate 35 designs/second for a behavioural description containing 41 primitive operations running on a Sun SPARCstation LX View full abstract»

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  • Uniqueness of solutions of networks with two terminal piecewise linear resistors

    Publication Year: 1994 , Page(s): 369 - 370
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    For networks containing resistors, independent-sources, gyrators, ideal transformers, diodes and other saturating monotone piecewise linear resistors, a new condition is proposed to guarantee uniqueness of solutions. This is both necessary and sufficient and is easy to test. It requires that the characteristics should satisfy a condition with the null vectors of the matrix of the linear part of the network whenever it is singular. Diodes with infinite reverse resistance are also allowed in the formulation View full abstract»

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  • Detection of weak Doppler signal in a strong carrier: an equivalent high-Q band-elimination filter

    Publication Year: 1994 , Page(s): 377 - 381
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    In the paper, weak Doppler-shifted components of reflected ultrasonic signals were measured following the application of continuous-wave ultrasound for the measurement of blood flow velocity using the Doppler effect. The component of the emitted frequency was suppressed by subtracting an extracted signal from the reflected signal obtained by nonlinear closed loops. Phase information of the signal was obtained with a phase-locked loop, while the amplitude was controlled by an integrated loop to make the component of the emitting frequency minimum after subtracting. In principle, the circuit could be considered as a sufficient narrow band-elimination filter. The Q of the fitter was 104-105; its elimination depth was larger than 40 dB; its frequency stability was better than 10-5 because the phase-locked loop used a crystal oscillator as the voltage-controlled oscillator. Applying this circuit to a telemetry system, an example of measuring carotid blood velocity in an exercising man is given in the paper View full abstract»

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  • Fast VLSI architectures using nonredundant multibit recoding for computing AY mod N

    Publication Year: 1994 , Page(s): 345 - 349
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    A recently proposed technique for multiplication using two-bit recoding, which does not require subtraction operations, is extended for fast AB mod N evaluation. Architectures considering 2, 4, 8 and 16 bit recoding are considered and compared regarding the ALU complexity and speed requirements View full abstract»

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  • Versatile voltage-controlled impedance configuration

    Publication Year: 1994 , Page(s): 414 - 416
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    A new configuration is introduced which, apart from realising the linearised voltage-controlled R, L and C elements (like a previously known scheme), can also realise ideal voltage-controlled frequency-dependent negative resistance (Z(s)=1/Ds2) and ideal voltage-controlled frequency-dependent negative conductance (Z(s)=Ms2) elements from the same topology. The new structure, employs the same number of opamps and a single FET, as in the earlier scheme but requires a relatively smaller number of passive elements and realises two additional types of elements. The validity and utility of the proposed configuration is demonstrated by experimental results View full abstract»

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  • New stability results for 2-D discrete systems based on the Fornasini-Marchesini state space model

    Publication Year: 1994 , Page(s): 427 - 432
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    New conditions for the internal stability of a 2-D discrete system described by the Fornasini-Marchesini (FM) local state-space model are presented. Further, the stability margin of a 2-D discrete system described by a (FM) state-space model is considered and methods to compute it or to obtain lower bounds are developed. These methods are based on the various forms of the Lyapunov equation for 2-D systems. Finally, a sufficient condition for the system to remain stable under parameter variations is presented View full abstract»

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  • Bit-serial digital filter architecture using RAM-based delay operators

    Publication Year: 1994 , Page(s): 371 - 376
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    Realisations of high-order bit-serial FIR digital filters can be dominated by the shift register stages required for the z-1 operators. This paper presents a new approach to the implementation of bit-serial delay operators based on the use of random access memory in combination with a data transformation process. Together these facilitate the storage and retrieval of serial data in a format compatible with conventional filter requirements. The method is described, an example given and area comparisons made for the cases of FPGA and standard cell ASIC technologies View full abstract»

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  • Experimental evaluation of capacitance tomographic flow imaging systems using physical models

    Publication Year: 1994 , Page(s): 357 - 368
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    An experimental method for evaluating the performance of capacitance tomographic flow imaging systems is described. Criteria are defined to describe the performance of these systems, namely spatial and permittivity resolution, accuracy (system errors) and signal to noise ratio. Static physical models simulating typical flow distribution patterns are used as standard test objects and The criteria are quantified by comparing the reconstructed images with the standards. Systems with 8 and 12 electrodes have been tested and the results compared to show the improvement obtained with the increased number of electrodes View full abstract»

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  • Noise analysis of second-order analogue active filters

    Publication Year: 1994 , Page(s): 350 - 356
    Cited by:  Papers (7)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    The output noise of continuous-time active filters is analysed in general terms by directly inserting device noise sources in an equivalent block diagram. This removes some of the restrictions imposed by previous methods of noise-source referral and permits more meaningful analytical optimisation. Design recommendations for minimising noise in a wide range of realisations then emerge. This allows performance comparisons of active-RC, active-R and OTA-C circuits View full abstract»

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  • Modular SPICE macromodel for operational amplifiers

    Publication Year: 1994 , Page(s): 417 - 420
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    A new operational-amplifier macromodel is presented based on a structured modular approach. The model performs well in comparative tests and parameter extraction from data sheets is far easier than previously published models View full abstract»

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  • Constant integer multiplication using minimum adders

    Publication Year: 1994 , Page(s): 407 - 413
    Cited by:  Papers (78)  |  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (532 KB)  

    A new method of formulating constant integer multiplication is presented. It requires fewer adders in general than a canonic signed-digit (CSD) representation. Graphs are used to illustrate multiplier implementation. A general suboptimal algorithm for the design of multipliers of any wordlength is presented. For 32-bit words, it achieves an average improvement of 26.6% over CSD. Rules for the generation of graphs with the minimum number of adders and subtracters are presented. An exhaustive search algorithm using these rules is described, and applied for word-lengths up to 12 bits. For 12-bit words, it was found that an average improvement of 16% over CSD is achievable View full abstract»

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