# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 56

Publication Year: 2017, Page(s):C1 - 2
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2017, Page(s): C2
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• ### The Charge Plasma n-p-n Impact Ionization MOS on FDSOI Technology: Proposal and Analysis

Publication Year: 2017, Page(s):3 - 7
Cited by:  Papers (1)
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In this paper, we propose the charge plasma n-p-n impact ionization MOS (I-MOS) on a lightly doped p-type silicon film using the charge plasma concept. The performance of the proposed device is exhaustively investigated using 2-D simulations. The proposed device does not have metallurgical junctions and needs no chemical doping for creating the source and drain regions. Therefore, the proposed dev... View full abstract»

• ### The 36 V Bipolar: $beta times V_{a} times text {fT} times text {BV} times text {JfT} times$ Linearity Tradeoff

Publication Year: 2017, Page(s):8 - 14
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This paper reports on the optimization of a 36 V complimentary bipolar design by using a new depletion mode field-effect architecture for the collector of the bipolar that greatly expands the boundary of the familiar tradeoffs. This achieves an n-p-n with a measured |β at 1 V x Va at 18 V| = |270 x 1100 V|, a JfT at 1 V = 28.7 μAμm-2, and |fT at 1 V x BV|... View full abstract»

• ### Small-Area Si Photovoltaics for Low-Flux Infrared Energy Harvesting

Publication Year: 2017, Page(s):15 - 20
Cited by:  Papers (2)
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Silicon photovoltaics are prospective candidates to power mm-scale implantable devices. These applications require excellent performance for small-area cells under low-flux illumination condition, which is not commonly achieved for silicon cells due to shunt leakage and recombination losses. Small area (1-10 mm2) silicon photovoltaic cells are studied in this paper, where performance im... View full abstract»

• ### Symmetric Operation in an Extended Back Gate JLFET for Scaling to the 5-nm Regime Considering Quantum Confinement Effects

Publication Year: 2017, Page(s):21 - 27
Cited by:  Papers (6)
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In this paper, we propose a double gate junctionless FET (DGJLFET) with an extended back gate (EBG) architecture for significantly improved performance in the sub-10-nm regime. Even for a channel length of 5 nm, we show using calibrated 2-D simulations that the EBG DGJLFET, when compared with the DGJLFET, exhibits: 1) an improved subthreshold swing; 2) a significantly low off-state leakage current... View full abstract»

• ### ESD Behavior of Tunnel FET Devices

Publication Year: 2017, Page(s):28 - 36
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For the first time, we present the electrostatic discharge (ESD) behavior of grounded gate tunnel FET (ggTFET) with detailed physical insight into the device operation, 3-D filamentation and failure under ESD stress conditions. Current as well as time evolution of the junction breakdown, device turn-ON, voltage snapback, and finally the unique failure mechanism is studied using both 2-D and 3-D te... View full abstract»

• ### Physical Differences in Hot Carrier Degradation of Oxide Interfaces in Complementary (n-p-n+p-n-p) SiGe HBTs

Publication Year: 2017, Page(s):37 - 44
Cited by:  Papers (3)
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This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the dama... View full abstract»

• ### An Analytical Model of Drain Current in a Nanoscale Circular Gate TFET

Publication Year: 2017, Page(s):45 - 51
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This paper presents an analytical model of drain current in a silicon tunnel FET with a circular gate (CG TFET). The method involves the bifurcation of the complete geometry into a rectangular gate conventional TFET, and the CG TFET itself based on the number of solvable regions of the CG TFET. The 2-D Poisson equation is solved on the regions of focus of each structure, and both the substructures... View full abstract»

• ### Impact of Fin Height and Fin Angle Variation on the Performance Matrix of Hybrid FinFETs

Publication Year: 2017, Page(s):52 - 57
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In this paper, we systematically examined the impact of fin height (HFin) and fin angle (θFin) on the ac performance parameters including total gate capacitance(Cgg), RC delay (CggVDD/ION), cutoff frequency (fT), energy (E), total power (PTotal), and leakage power (PLeakage) of hybrid FinFETs ... View full abstract»

• ### Nanoscale FETs Simulation Based on Full-Complex-Band Structure and Self-Consistently Solved Atomic Potential

Publication Year: 2017, Page(s):58 - 65
Cited by:  Papers (1)
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An improved simulation scheme for investigating the performance of nanoscale FETs is developed in this paper. The total current of the MOSFET consists of two main components: thermionic current above the top of barrier of the channel calculated by ballistic approach and tunneling current computed by Wentzel-Kramer-Brillouoin approximation based on a full-complex-band structure. Furthermore, to get... View full abstract»

• ### Analytical Drain Current Compact Model in the Depletion Operation Region of Short-Channel Triple-Gate Junctionless Transistors

Publication Year: 2017, Page(s):66 - 72
Cited by:  Papers (1)
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A new charge-based analytical compact model for the drain current of junctionless (JL) triple-gate MOSFETs is presented, which includes the short-channel effects, the saturation velocity overshoot, the series resistance, and the mobility degradation effects. The proposed model consists of a single analytical equation that covers the depletion operation region in which the bulk conduction determine... View full abstract»

• ### Field-Related Failure of GaN-on-Si HEMTs: Dependence on Device Geometry and Passivation

Publication Year: 2017, Page(s):73 - 77
Cited by:  Papers (2)
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This paper reports on an extensive analysis of the breakdown of GaN-based Schottky-gated HEMTs submitted to high-voltage stress. The analysis was carried out on transistors with different lengths of the drain-side gatehead (LGH), corresponding to different levels of electric field across the SiN passivation. Based on dc measurements, 2-D simulations, and optical analysis, we demonstrate... View full abstract»

• ### Characterization of AlGaN/GaN HEMTs Using Gate Resistance Thermometry

Publication Year: 2017, Page(s):78 - 83
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In this paper, gate resistance thermometry (GRT) was used to determine the channel temperature of AlGaN/GaN high electron-mobility transistors. Raman thermometry has been used to verify GRT by comparing the channel temperatures measured by both techniques under various bias conditions. To further validate this technique, a thermal finite-element model has been developed to model the heat dissipati... View full abstract»

• ### Influence of the Heterojunction Spacer on the Performance of AlGaN/GaN/AlGaN Resonant Tunneling Diodes

Publication Year: 2017, Page(s):84 - 88
Cited by:  Papers (3)
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We report on a simulation for an aluminum gallium nitride (AlGaN)/gallium nitride (GaN) resonant tunneling diode (RTD) with a step heterojunction emitter spacer (SHES) at room temperature. An SHES and low Al component barriers were introduced in to AlGaN/GaN RTDs to improve the electronic injection efficiency in to the emitter, reduce the transit time in the collector depletion region, and achieve... View full abstract»

• ### Enhancement of $f_{\mathrm {max}}$ to 910 GHz by Adopting Asymmetric Gate Recess and Double-Side-Doped Structure in 75-nm-Gate InAlAs/InGaAs HEMTs

Publication Year: 2017, Page(s):89 - 95
Cited by:  Papers (3)
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A high maximum frequency of oscillation (fmax) of 910 GHz was achieved at InAlAs/InGaAs highelectron mobility transistors (HEMTs) with a relatively long gate length (LG) of 75 nm by adopting an asymmetric gate recess and a double-side-doped structure. The fmax improved significantly by extending the drain-side gate recess length (LRD) to 250 nm; meanwhil... View full abstract»

• ### Scalable GaSb/InAs Tunnel FETs With Nonuniform Body Thickness

Publication Year: 2017, Page(s):96 - 101
Cited by:  Papers (1)
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GaSb/InAs heterojunction tunnel FETs are strong candidates in building future low-power ICs, as they could provide both steep subthreshold swing and large on-state current (ION). However, at short-channel lengths, they suffer from large tunneling leakage originating from the small bandgap and small effective masses of the InAs channel. As proposed in this paper, this problem can be sign... View full abstract»

• ### Iso-Trapping Measurement Technique for Characterization of Self-Heating in a GaN HEMT

Publication Year: 2017, Page(s):102 - 108
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The temperature response of field-effect transistors (FETs) to instantaneous power dissipation has been shown to be significant at high frequencies, even though the self-heating process has a very slow time constant. This affects intermodulation at high frequencies. A major difficulty in characterizing the self-heating process in microwave FETs is to differentiate between the self-heating and char... View full abstract»

• ### Experimental Studies of the Frequency Dependence of the Low-Barrier Mott Diode Impedance

Publication Year: 2017, Page(s):109 - 114
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We study the microwaave impedance of low-barrier Mott diodes with a δ-doped layer near the metal contact. Parameters of the elements of the diode equivalent circuit are determined and their dependences on the dc bias voltage are examined. The effects of injection of electrons into the i layer and their time delay in the potential well of the δ layer under a forward bias are discussed... View full abstract»

• ### Combining High Hole Concentration in p-GaN and High Mobility in u-GaN for High p-Type Conductivity in a p-GaN/u-GaN Alternating-Layer Nanostructure

Publication Year: 2017, Page(s):115 - 120
Cited by:  Papers (2)
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p-GaN/u-GaN alternating-layer nanostructures are grown with molecular beam epitaxy to show a low p-type resistivity level of 0.038 Ω-cm. The obtained low resistivity is due to the high hole mobility in the u-GaN layers, which serve as effective transport channels of holes diffused from the neighboring p-GaN layers. The Mg doping in a thin p-GaN layer can lead to a high Mg-doping concentrati... View full abstract»

• ### Tunneling Negative Differential Resistance-Assisted STT-RAM for Efficient Read and Write Operations

Publication Year: 2017, Page(s):121 - 129
Cited by:  Papers (3)
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The adoption of spin-transfer torque random access memory (STT-RAM) into nonvolatile memory systems faces three major obstacles: high write energy, low sensing margin, and high read disturbance. Many designs have been suggested to resolve each of these challenges separately and at the cost of significant overhead. We propose a single low-overhead solution to all these problems without changing the... View full abstract»

• ### Feasibility of InxGa1–xAs High Mobility Channel for 3-D NAND Memory

Publication Year: 2017, Page(s):130 - 136
Cited by:  Papers (1)
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Epitaxial InxGa1-xAs is grown by metal organic vapor phase epitaxy as replacement of polycrystalline silicon (Si) channel for high-density 3-D NAND memory applications. The most challenging steps to integrate InxGa1-xAs are thoroughly discussed; their impact on the electrical performances are investigated and the tunnel oxide (TuOx) quality is assessed. ... View full abstract»

• ### Self-Heating During submicrosecond Current Transients in Pr0.7Ca0.3MnO3-Based RRAM

Publication Year: 2017, Page(s):137 - 144
Cited by:  Papers (5)
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In filamentary RRAM, the role of self-heating in set/reset (by ion transport) is well established. However, in nonfilamentary Pr0.7Ca0.3MnO3 (PCMO) RRAM, self-heating during set/reset has not been explored. Recently, we have shown self-heating to explain nonlinearity in dc IV characteristics. In this paper, we present the observation of self-heating using transient... View full abstract»

• ### Analysis of the Meyer-Neldel Rule Based on a Temperature-Dependent Model for Thin-Film Transistors

Publication Year: 2017, Page(s):145 - 152
Cited by:  Papers (1)
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Based on the Pao-Sah model and considering the double exponential distribution of traps density of states (DOS) in the bandgap, a unified drain current model is derived for thin-film transistors (TFTs). It is verified by fitting experimental I-V characteristics of both a-InGaZnO TFTs and two types of polycrystalline Si TFTs of different technologies, measured at different drain voltages and temper... View full abstract»

• ### The Effect of Drain Bias Stress on the Instability of Turned-OFF Amorphous HfInZnO Thin-Film Transistors Under Light Irradiation

Publication Year: 2017, Page(s):153 - 158
Cited by:  Papers (1)
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A comprehensive study was done regarding stabilities under simultaneous stress of light and negative gate bias (VG)/positive drain bias (VD) in amorphous hafnium-indium-zinc-oxide thin-film transistors. Negative threshold voltage (Vth) shift was observed in transfer characteristics after the stress. Through the consecutive stresses of (VG = -5V, VD<... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy