Issue 11 • Date Nov 1994
Filter Results
Displaying Results 1 - 15 of 15
-
A high-performance SI memory cell
|
PDF (224 KB)
-
-
-
-
-
A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources
|
PDF (536 KB)
-
-
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory
|
PDF (612 KB)
-
A 30-ns cycle time 4-Mb mask ROM
|
PDF (532 KB)
-
-
-
Accurate SI filters using RGC integrators
|
PDF (808 KB)
-
CMOS chip for invasive ultrasound imaging
|
PDF (672 KB)
-
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM
|
PDF (636 KB)
-
A 32-bank 256-Mb DRAM with cache and TAG
|
PDF (564 KB)
Aims & Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.
Meet Our Editors
Editor-in-Chief
Un-Ku Moon
Oregon State University, EECS


