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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 21 of 21

Publication Year: 2016, Page(s):C1 - C4
| PDF (410 KB)
• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2016, Page(s): C2
| PDF (86 KB)
• ### An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC

Publication Year: 2016, Page(s):3373 - 3386
Cited by:  Papers (1)
| | PDF (3586 KB) | HTML

Power gating (PG) is one of the most effective techniques to reduce the leakage power in multiprocessor system-on-chips (MPSoCs). However, the power-mode transition during the PG period of an individual processing unit (PU) will introduce serious power/ground (P/G) noise to the neighboring PUs. As technology scales, the P/G noise problem becomes a severe reliability threat to MPSoCs. At the same t... View full abstract»

• ### Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip

Publication Year: 2016, Page(s):3387 - 3400
| | PDF (4355 KB) | HTML

We propose an approach for computing the end-to-end delay bound of individual variable bit-rate flows in an First Input First Output multiplexer with aggregate scheduling under weighted round robin (WRR) policy. To this end, we use a network calculus to derive per-flow end-to-end equivalent service curves employed for computing least upper delay bounds (LUDBs) of the individual flows. Since the re... View full abstract»

• ### Emulation-Based Analysis of System-on-Chip Performance Under Variations

Publication Year: 2016, Page(s):3401 - 3414
| | PDF (4008 KB) | HTML

The scaling of integrated circuits into the nanometer regime has led to variations emerging as a primary design concern. Most efforts in the area of variation-tolerant design have focused on the physical, circuit, and logic levels of abstraction. However, inevitable increases in the magnitude of variations with scaling have elevated them to a design concern that must be addressed starting at the s... View full abstract»

• ### Effective Radii of On-Chip Decoupling Capacitors Under Noise Constraint

Publication Year: 2016, Page(s):3415 - 3423
Cited by:  Papers (4)
| | PDF (2869 KB) | HTML

As the clock frequency of a chip increases, the on-chip decoupling capacitor must be placed closer to the load to be effective. A method of efficiently defining the location of capacitor placement to meet specified noise limits is presented. Based on a single RL line model for the power distribution system, charging radius of the decoupling capacitor is calculated under the constraint of the targe... View full abstract»

• ### A Highly Scalable Optical Network-on-Chip With Small Network Diameter and Deadlock Freedom

Publication Year: 2016, Page(s):3424 - 3436
| | PDF (2661 KB) | HTML

To increase the performance of chip multiprocessors, optical network-on-chip (ONoC) becomes promising because of its high bandwidth and low energy consumption. In this paper, we propose an architecture called RPNoC (Ring-based Packet-switched NoC), which uses few optical devices. Specifically, Single-waveguide RPNoC employs only one waveguide. Multiwaveguide RPNoC introduces space division multipl... View full abstract»

• ### Architecture of Ring-Based Redundant TSV for Clustered Faults

Publication Year: 2016, Page(s):3437 - 3449
| | PDF (6891 KB) | HTML

Three-dimensional integrated circuits (3-D-ICs) that employ the through-silicon vias (TSVs) vertically stacking multiple dies provide many benefits, such as high density, high bandwidth, and low power. However, the fabrication and bonding of TSVs may fail because of many factors, such as the winding level of the thinned wafers, the surface roughness and cleanness of silicon dies, and bonding techn... View full abstract»

• ### Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes

Publication Year: 2016, Page(s):3450 - 3459
Cited by:  Papers (4)
| | PDF (2433 KB) | HTML

Optical interconnects for system-in-package applications can be designed for various bit rates. In this paper, an optimization study is conducted to find the optimal parameters for electrooptical links, based on a silicon photonic technology. We focus on the bit rate to achieve highest possible power efficiencies. This paper takes all the elements of an electrooptical link into account: serializat... View full abstract»

• ### Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array

Publication Year: 2016, Page(s):3460 - 3467
Cited by:  Papers (4)
| | PDF (2146 KB) | HTML

The 3-D integration of resistive switching random access memory (RRAM) array is attractive for low-cost and high-density nonvolatile memory application. In this paper, the design tradeoffs of select transistor drivability, RRAM device characteristics, such as switching current (IW), ON/OFF-state resistance (RON/ROFF), and I-V nonlinearity ratio, interconnect materi... View full abstract»

• ### System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators

Publication Year: 2016, Page(s):3468 - 3476
Cited by:  Papers (3)
| | PDF (2375 KB) | HTML

In this paper, we study two different ON-chip power delivery schemes, namely, fully integrated voltage regulator (FIVR) and low-dropout regulator (LDO), and analyze their effect on total system power under process variation, assuming a realistic dynamic voltage-frequency scaling (DVFS) system. The impact of different task scheduling algorithms on the overall system power was also analyzed. We find... View full abstract»

• ### A High-SNR Projection-Based Atom Selection OMP Processor for Compressive Sensing

Publication Year: 2016, Page(s):3477 - 3488
Cited by:  Papers (1)
| | PDF (3902 KB) | HTML

Compressive sensing (CS) has recently become a critical technique to reduce the high computational cost of signal processing systems. One of the main signal processing modules of CS systems is the signal reconstruction processor. Orthogonal matching pursuit (OMP) is one of the main signal reconstruction algorithms because of its low complexity and high regularity compared with the greedy $l1$ algo... View full abstract»

• ### Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Publication Year: 2016, Page(s):3489 - 3498
| | PDF (2181 KB) | HTML

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM relays have been significantly investigated as highly energy-efficient design solutions. A major shortcoming of NEMs preventing their widespread use... View full abstract»

• ### A Multimode Area-Efficient SCL Polar Decoder

Publication Year: 2016, Page(s):3499 - 3512
Cited by:  Papers (6)
| | PDF (3994 KB) | HTML

Polar codes are of great interest, since they are the first provably capacity-achieving forward error correction codes. To improve throughput and to reduce decoding latency of polar decoders, maximum likelihood (ML) decoding units are used by successive cancellation list (SCL) decoders as well as SC decoders. This paper proposes an approximate ML (AML) decoding unit for SCL decoders first. In part... View full abstract»

• ### 5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications

Publication Year: 2016, Page(s):3513 - 3525
Cited by:  Papers (4)
| | PDF (4691 KB) | HTML

This paper presents a 5-bit noninterleaved time-based analog-to-digital converter (ADC), which operates at a 5-GS/s rate. The ADC is designed for the use in radio-astronomy telescopes, for which time interleaving is not acceptable. The ADC employs a dynamic, differential voltage-to-time converter, a folded-flash time-to-digital converter (TDC), and calibration circuitry. To generate reference dela... View full abstract»

• ### Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels

Publication Year: 2016, Page(s):3526 - 3537
Cited by:  Papers (4)
| | PDF (2010 KB) | HTML

Text mining is a growing field of applications, which enables the analysis of large text data sets using statistical methods. In recent years, exponential increase in the size of these data sets has strained existing systems, requiring more computing power, server hardware, networking interconnects, and power consumption. For practical reasons, this trend cannot continue in the future. Instead, we... View full abstract»

• ### Optimizing the Implementation of SEC–DAEC Codes in FPGAs

Publication Year: 2016, Page(s):3538 - 3542
| | PDF (885 KB) | HTML

Single error correction and double-adjacent error correction (SEC-DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, such as space or avionics. ECC encoders and decoders have a regular structure that makes it easier to accommodate them into field-programmable gate... View full abstract»

• ### Asymmetrical Dead-Time Control Driver for Buck Regulator

Publication Year: 2016, Page(s):3543 - 3547
| | PDF (1788 KB) | HTML

This brief presents an asymmetrical dead-time control driver (ASDTCD) for synchronous buck converter operating in the continuous conduction mode. Dead-time control is an important metric for improving the efficiency of switching mode power regulator. Without an additional circuit, the proposed ASDTCD can generate dead time by controlling the slope for the output signal of the driver. The proposed ... View full abstract»

• ### A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring

Publication Year: 2016, Page(s):3548 - 3552
| | PDF (1752 KB) | HTML

This brief presents a built-in self-calibration (BISC) technique for minimization of the total jitter in bang-bang all-digital phase-locked loops (ADPLLs). It is based on the addition of a monitoring phase-frequency detector (PFD) with tunable delay cells for the reference clock and the divider clock and a counter for this PFD output signal. This allows for on-chip binary comparison of the jitter ... View full abstract»

• ### 2016 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 24

Publication Year: 2016, Page(s):1 - 44
| PDF (381 KB)
• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2016, Page(s): C3
| PDF (62 KB)

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu