# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 80

Publication Year: 2016, Page(s):C1 - 4555
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2016, Page(s): C2
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• ### Changes in the Editorial Board

Publication Year: 2016, Page(s): 4556
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• ### Kudos to Our Reviewers

Publication Year: 2016, Page(s): 4557
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The ability of the IEEE Transactions on Electron Devices (T-ED) to publish quality papers has always been and will continue to be critically dependent upon the competence, diligence, and generosity of reviewers who voluntarily contribute their time for this purpose. The T-ED Editorial Board and I are well aware of our dependence on quality reviews and wish to acknowledge and recognize the individu... View full abstract»

• ### Golden List of Reviewers for 2016

Publication Year: 2016, Page(s):4558 - 4590
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• ### Single Transistor-Based Methods for Determining the Base Resistance in SiGe HBTs: Review and Evaluation Across Different Technologies

Publication Year: 2016, Page(s):4591 - 4602
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The base series resistance is an important parameter for bipolar junction transistors and heterojunction bipolar transistor (HBTs). Although many methods have been proposed for its experimental determination, their results vary significantly. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations including different device types,... View full abstract»

• ### RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors

Publication Year: 2016, Page(s):4603 - 4609
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Finger-type shallow trench isolation (finger STI) drain extended MOS transistors are fabricated and its electrical characteristics is studied. Polyplate on a finger STI served as a reduced surface field is adopted to enhance breakdown voltage (BV) by reducing the effective doping concentration of the drain extension (DE) finger. The conformal mapping method, which relates the reduction of the dopi... View full abstract»

• ### Design of Poly-Si Junctionless Fin-Channel FET With Quantum-Mechanical Drift-Diffusion Models for Sub-10-nm Technology Nodes

Publication Year: 2016, Page(s):4610 - 4616
Cited by:  Papers (3)
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In this paper, a junctionless FinFET (JLFinFET) having polycrystalline-silicon (poly-Si) channel has been optimally designed and characterized by stringent device simulation aiming 10-nm-and-beyond Si technology node. Replacing the silicon-on-insulator platform employed for realizing the JLFETs in most cases by bulk Si substrate featuring deposited oxide and poly-Si channel would warrant highly co... View full abstract»

• ### 3-D Quasi-Atomistic Model for Line Edge Roughness in Nonplanar MOSFETs

Publication Year: 2016, Page(s):4617 - 4623
Cited by:  Papers (1)
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As the physical sizes of devices have been scaled down, the negative impact of process-induced random variation on device performance has increased; therefore, there is an urgent demand for advanced simulation methods for variation. In this paper, a 3-D quasi-atomistic simulation methodology for line edge roughness (LER) in nonplanar devices, such as FinFETs and gate-all-around (GAA) FETs, is prop... View full abstract»

• ### TCAD-Based Predictive NBTI Framework for Sub-20-nm Node Device Design Considerations

Publication Year: 2016, Page(s):4624 - 4631
Cited by:  Papers (5)
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The kinetics of trap generation during negative-bias temperature instability (NBTI) stress in pMOSFETs, as governed by the double interface H-H2 reaction-diffusion (RD) model, is incorporated for the first time in a commercial technology computer-aided design (TCAD) software, and used for simulating degradation in various device architectures. The calibrated TCAD framework is shown to successfully... View full abstract»

• ### Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching $1 \times 10^{-9}$ Ohm-cm2

Publication Year: 2016, Page(s):4632 - 4641
Cited by:  Papers (4)
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In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSix) and achieve ultralow contact resistivity (ρc) of (1.3 - 1.5) × 10-9 &#x... View full abstract»

• ### Chord-Fractal Capacitor in CMOS Technology

Publication Year: 2016, Page(s):4642 - 4646
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The proposed chord-fractal pattern has a significant impact on IC capacitor, increasing the capacitance within a limited chip area. To reduce the device area, this paper presents a modified fractal algorithm. This proposed algorithm uses various initiators to perform chord iteration on the unit cell. The iteration procedure automatically generates an area-saving fractal layout of IC capacitor. To ... View full abstract»

• ### V2O5 MISFETs on H-Terminated Diamond

Publication Year: 2016, Page(s):4647 - 4653
Cited by:  Papers (2)
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We report for the first time on the dc and RF performance of novel MISFETs fabricated on hydrogen-terminated (H-terminated) single crystal diamond film using vanadium pentoxide (V2O5) as insulating material. The active devices were characterized in terms of static I-V characteristics and static transconductance as well as of S-parameters for the calculation of the maximum cut... View full abstract»

• ### Transient and Static Hybrid-Triggered Active Clamp Design for Power-Rail ESD Protection

Publication Year: 2016, Page(s):4654 - 4660
Cited by:  Papers (3)
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A transient and static hybrid-triggered active clamp is proposed in this paper. By skillfully incorporating different detection mechanisms, the proposed clamp achieves enhanced static electrical overstress protection capability over the transient one. Furthermore, the proposed clamp achieves improved electrostatic discharge reaction speed in both human body model and charged device model events ov... View full abstract»

• ### A Short Channel Double-Gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect

Publication Year: 2016, Page(s):4661 - 4667
Cited by:  Papers (3)
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A new model to capture the physics of short channel double-gate junctionless transistor (DGJT) has been developed. By solving the 2-D Poisson's equation, the channel potential solution is obtained for both the physical channel and the dynamic channel extension to the source and drain. This dynamic change in channel boundary in DGJT has a strong impact on the performance of junctionless transistor,... View full abstract»

• ### Sub-0.2 V Impact Ionization in Si n-i-p-i-n Diode

Publication Year: 2016, Page(s):4668 - 4673
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Sub-0.6 V experimental demonstration of impact ionization (II) is a challenge in Si devices. We propose a new n+-i-δ p+-i-n+ diode structure where II current is integrated as stored charge, which strongly affects the output current. The device was fabricated and measured current-voltage was compared with “ideal” TCAD-based drift diffusion simul... View full abstract»

• ### Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

Publication Year: 2016, Page(s):4674 - 4677
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In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with Leff= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized... View full abstract»

• ### Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

Publication Year: 2016, Page(s):4678 - 4684
Cited by:  Papers (4)
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In this paper, we propose and investigate the high-performance and low-power design space of nonhysteretic negative capacitance (NC) MOSFETs for the 14-nm node based on the calibrated simulations using an experimental gate-stack with PZT ferroelectric to obtain the NC effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to e... View full abstract»

• ### Quasi-Ballistic $\Gamma$ - and L-Valleys Transport in Ultrathin Body Strained (111) GaAs nMOSFETs

Publication Year: 2016, Page(s):4685 - 4692
Cited by:  Papers (1)
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We carefully scrutinize the potential of ultrathin body strained (111) GaAs MOSFETs to achieve better performance than other GaAs-based channel FETs at scaled channel length and with relaxed thickness requirements, thanks to L-valleys enhanced density-of-states (DoS) and carrier transport. Calibrated multi-subband Monte Carlo simulations including scattering provide the modeling framework necessar... View full abstract»

• ### Low-Temperature ICP-CVD SiNx as Gate Dielectric for GaN-Based MIS-HEMTs

Publication Year: 2016, Page(s):4693 - 4701
Cited by:  Papers (3)
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SiNx deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD) technique at low temperature (70 °C) was investigated as gate dielectric for AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). Besides significant reduction in gate leakage current, the MIS-HEMTs showed improvement in drain current characteristics, 2DEG channel m... View full abstract»

• ### The Role of Barrier Transport and Traps in the Tradeoff Between Low OFF-State Leakage Current and Improved Dynamic Stability of AlGaN/GaN HFETs

Publication Year: 2016, Page(s):4702 - 4706
Cited by:  Papers (1)
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A tradeoff behavior between low Schottky gate leakage current and improved dynamic stability of AlGaN/GaN heterostructure FETs was previously reported, and was attributed to variations in the metal/semiconductor interface properties. Here, we show that a tradeoff behavior is found in transistors and gated van der Pauw test structures that were fabricated on the same wafer, and underwent identical ... View full abstract»

• ### An Analytical Model of MOS Admittance for Border Trap Density Extraction in High- $k$ Dielectrics of III–V MOS Devices

Publication Year: 2016, Page(s):4707 - 4713
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In this paper, we have developed a straightforward MOS admittance-based technique for defect density extraction, utilizing analytical equations for MOS capacitors with border traps (BTs). We show that these equations can provide an efficient technique to obtain the BT density directly from the measured data without any requirement of numerically involved techniques. This is demonstrated by applyin... View full abstract»

• ### Investigation of Multilayer TiNi Alloys as the Gate Metal for nMOS In0.53Ga0.47As

Publication Year: 2016, Page(s):4714 - 4719
Cited by:  Papers (4)
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To achieve low power consumption for CMOS devices, the gate metals must have effective work function (EWF) aligned with the band edges of the channel material and have a small WF variation (WFV). The multilayer TiNi alloys have been successfully applied as the gate metals for HfO2/In0.53Ga0.47As MOS devices in this paper. The EWF of TiNi alloys was found to increas... View full abstract»

• ### Electrothermal Characterization in 3-D Resistive Random Access Memory Arrays

Publication Year: 2016, Page(s):4720 - 4728
Cited by:  Papers (1)
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Resistive random access memory (RRAM) is a promising candidate for next generation nonvolatile memory technology. In this paper, electrothermal simulation in 3-D RRAM arrays is performed by using our in-house developed finite difference algorithm, which is validated by comparing the simulated temperature distribution with its counterpart obtained by commercial software. Both crossbar RRAM array an... View full abstract»

• ### Finite Element Modeling of Fowler–Nordheim Program-Erase Process in High- $k$ Interpoly Dielectric Flash Memories

Publication Year: 2016, Page(s):4729 - 4736
Cited by:  Papers (3)
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The program/erase process in floating gate (FG) flash memory devices is modeled by considering sequential quantum tunneling of electrons and taking into account quantum confinement in the channel and FG. We precisely determine location of quasi-bound or decaying quantum states in the inversion layer and in FG comprising a nanocrystal (NC) layer, and compute their lifetime by finding the complex ei... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy