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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct 1994

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Displaying Results 1 - 25 of 31
  • Short channel characteristics of Si MOSFET with extremely shallow source and drain regions formed by inversion layers

    Page(s): 1831 - 1836
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    The influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFET's are experimentally investigated. These extremely shallow junctions are realized in MOSFET's with a triple-gate structure. Two subgates formed as side-wall spacers of a main gate induce inversion layers which work as the virtual source and drain. Significant improvement in threshold voltage roll-off and punchthrough characteristics are obtained in comparison with conventional MOSFET's whose junctions are formed by ion implantation: threshold voltage roll off is suppressed down to a physical gate length of 0.1 μm while punchthrough is suppressed down to 0.07 μm, the minimum pattern size delineated. It is also demonstrated experimentally that the carrier concentrations in the source and drain do not have any influence on the short channel effects View full abstract»

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  • Measured DC performance of large arrays of silicon field emitters

    Page(s): 1866 - 1870
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    Large arrays of silicon field emitters are being produced at MCNC for use in RF and microwave amplifiers and other high-intensity electron beam source applications. Significant levels of both total emitted current (up to 7 mA) and current density (7 A/cm2) are obtained using gate electrode potentials less than 250 V with emission efficiencies as high as 99%. Large arrays of field emitters are operated at 100% duty cycle for over 18 hours. Data from devices with 1197 and 232 630 tips are presented, along with electrical yield statistics for arrays of other sizes View full abstract»

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  • Characteristics of polycrystalline-Si thin film transistors fabricated by excimer laser annealing method

    Page(s): 1876 - 1879
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    The electrical characteristics of excimer laser annealed (ELA) polycrystalline-Si thin film transistors (poly-Si TFT's) were investigated. These results were compared to those of poly-Si TFT fabricated by solid phase crystallization (SPC). From the temperature dependence of the drain current, the activation energies of n-type poly-Si TFT's were obtained. The activation energies have negative values under the gate voltage from 0 to 5 V. The negative activation energy together with small threshold voltage (Vth) are the main characteristics of ELA poly-Si TFT. Temperature dependencies of V th, and field effect mobility are very similar to those of SPC. From these results, it is concluded that the trap state density of ELA poly-Si TFT is very small and the electrical characteristics can be explained by the band tail states localized at the grain boundary View full abstract»

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  • Investigation of negative differential resistance phenomena in GaSb/AlSb/InAs/GaSb/AlSb/InAs structures

    Page(s): 1734 - 1741
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    The negative differential resistance (NDR) phenomena were observed in GaSb/AlSb/InAs/-GaSb/AlSb/InAs resonant interband tunnel structures. Electrons have resonantly achieved interband tunneling through the InAs/GaSb broken-gap quantum well. The InAs well width causes significant variations of the peak current density and NDR behaviors. The peak current density varies exponentially with the AlSb barrier thickness. The multiple NDR behavior was observed with appropriate InAs well and AlSb barrier thicknesses, e.g., 30 Å thick AlSb barrier and 240 Å wide InAs well. Only single negative resistance has, otherwise, been seen. The three-band model was used to interpret the effect of the InAs well and AlSb barrier on the current-voltage characteristics of GaSb/AlSb/InAs/GaSb/AlSb/InAs structures View full abstract»

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  • An evaluation of super-steep-retrograde channel doping for deep-submicron MOSFET applications

    Page(s): 1880 - 1882
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    Performance and reliability of deep-submicron MOSFET's employing super-steep-retrograde (SSR) channel doping configurations are examined using self-consistent Monte Carlo and drift-diffusion simulations. It is found that SSR channel doped MOSFET's provide increased current drive and reduced threshold voltage shift when compared with conventional MOSFET structures. However, they also display a relatively higher substrate current and interface state generation rate. The physical mechanisms of performance enhancement/degradation and design tradeoffs for SSR channel doped MOSFET's are discussed View full abstract»

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  • Analysis and optimal design of semi-insulator passivated high-voltage field plate structures and comparison with dielectric passivated structures

    Page(s): 1856 - 1865
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    The influences of the field oxide thickness and the junction depth on the breakdown voltage of semi-insulator passivated planar junctions with the field plate are investigated using a 2D simulator. This is done by analyzing the two extreme situations: the planar junction with an infinitely long field plate, and the deep-depleted MOS structure having a finite size. This rather unconventional approach has offered a new physical insight into the role of the metal field plate and has revealed that the severe field crowding associated with a shallow planar junction can be greatly suppressed by using a thin field oxide. The breakdown voltage and the optimal field oxide thickness of the semi-insulator passivated field plate structures remain nearly constant over a wide variation in the junction depth, and therefore such structures are attractive for realizing high-voltages in vertical devices fabricated by low-voltage IC technology. The influences of the field plate width and the inter-electrode spacing are studied by the conventional approach, and a simple and widely applicable design guideline is given for both the nonpunchthrough and the punchthrough type structures. The influence of the surface charge in the range 0 to 1012 cm-2 is found to be negligible. The semi-insulator passivated and the dielectric passivated field plate structures are compared under optimal conditions. This suggests that the semi-insulator passivated structures are attractive when thin field oxide and a shallow planar junction are needed and that the dielectric passivated structures are better when compactness is desired View full abstract»

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  • Electronic transport through a kink in an electron waveguide

    Page(s): 1843 - 1847
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    The current-voltage dependence corresponding to electronic transport through a kink in an electronic waveguide is analyzed. No phase breaking dissipation mechanisms are considered, but the effects of the Coulomb interaction are included through a self consistent approximation. The results indicate very nonlinear transport properties, including negative differential resistance and bistability View full abstract»

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  • Characterization of the cell leakage of a stacked trench capacitor (STT) cell

    Page(s): 1801 - 1805
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    The cell leakage of a stacked trench capacitor (STT) cell has been investigated. The major leakage mechanisms of the STT are trench-to-trench leakage, trench junction leakage, and LOCOS isolation leakage. It is shown that compared to a conventional trench capacitor, the trench-to-trench leakage current is reduced and high punchthrough voltage is obtained. Therefore, the trench-to-trench spacing can be reduced 0.1 μm shorter than that of the trench capacitor. These reductions result from the STT structure itself. The surface leakage current, which is the dominant leakage current in the trench capacitor, does not flow in the STT. This paper also describes the effect of the sidewall damage caused by trench etching on the trench junction leakage. Reactive ion etching (RIE) produces deep levels just beneath the trench surface. But, the trench junction of the STT is not influenced by these deep levels because the trench surface is covered by a n-diffused layer. This paper also investigates the relationship between the cell leakage and the retention time. At DRAM operation temperatures, LOCOS isolation leakage is dominant rather than trench junction leakage. Therefore, the deeper trench can increase the storage capacitance and improve the retention time View full abstract»

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  • Hot carrier induced bipolar transistor degradation due to base dopant compensation by hydrogen: theory and experiment

    Page(s): 1824 - 1830
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    New experimental and analytical results are presented which show that extrinsic and intrinsic base dopant compensation by hydrogen is responsible for large changes in the bipolar transistor parameters of emitter-base breakdown voltage (Vebo), forward collector current (Ic) and series base resistance (Rbx) when such transistors are operated under avalanche and inverted mode stress conditions. A new physical model has been developed to explain the observed changes in Vebo and Ic as a function of stress time, and the analytical results are shown to be well correlated with the experimental data. Lastly, the effects of degradation on transistor voltage gain bandwidth (fmax) and emitter coupled bipolar comparator delay (τdelay) are assessed and discussed in terms of circuit performance degradation View full abstract»

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  • Origin and modeling of the frequency dependent output conductance in microwave GaAs MESFET's with buried p layer

    Page(s): 1725 - 1733
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    This paper presents the results of measurements and modeling of the frequency dependent output admittance of GaAs microwave MESFET's with and without the buried p layer constructions. The output conductance of devices without the buried p layer shows a transition from a low to a higher value typically within the frequency range of 10 Hz-100 Hz at 300 K, and 10 KHz-100 KHz at 367 K. The shape of this transition is determined by the presence of multiple deep levels at the channel-substrate interface, while the magnitude of the higher value of the output conductance is determined by the transconductance of the substrate-controlled parasitic FET. The addition of a buried p layer beneath the channel region results in a parasitic n-p-n bipolar transistor without completely eliminating the parasitic FET action. Results of our study show that the combined effects of these two parasitic transistors on the output conductance of the buried p layer device becomes relatively independent of frequency above 10 Hz at 300 K. However, at higher temperatures the frequency dispersion of the output conductance becomes significant at frequencies above 10 Hz. At low frequencies the parasitic FET causes a very high output capacitance, whereas the parasitic BJT action causes a high negative output capacitance. For the purpose of modeling of the output admittance, this paper indicates how the parameters of the parasitic FET and BJT can be determined by direct measurements on the MESFET's. The paper also suggests how the parameters of these parasitic transistors can be tailored by possible device structural changes, in order to achieve MESFET's with negligible dispersion of output conductance View full abstract»

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  • Significant time constants defined by high-current charge dynamics in advanced silicon-based bipolar transistors

    Page(s): 1796 - 1800
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    Analytical expressions for the time constants in advanced silicon-based bipolar transistors defined by the charge dynamics in the base-collector junction space-charge region (τC) and by the charge modulation in the quasi-neutral base (τBM) are derived based on an accounting for the high-current-induced perturbation of the space-charge region. The derivations show that voltage drops in the intrinsic and extrinsic collector regions and in the extrinsic emitter region are important in defining τC and τBM, and that τBM is approximately proportional to collector-current density. Application of the results to an aggressive SiGe-base HBT technology shows that τC and τBM are comparable to the base transit time, and hence that they are significant in defining high-current speed of the HBT View full abstract»

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  • Design, fabrication, and characterization of striped channel HEMT's

    Page(s): 1716 - 1724
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    A theoretical and experimental study of striped channel HEMT's is presented in this paper. The source to drain region of striped channel HEMT's is divided into a number of narrow conducting channels. Hence, the control of the charges by the Schottky gate is two-dimensional, which improves the transconductance value. Striped channel HEMT's have been successfully realized and characterized. The experimental results agree well with the theoretical ones. The structure of an optimized device is then proposed View full abstract»

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  • Effects of deposition temperature on the oxidation resistance and electrical characteristics of silicon nitride

    Page(s): 1747 - 1752
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    A study was made of the effects of deposition temperature on the oxidation resistance and electrical characteristics of silicon nitride. It was found that silicon nitride below a certain limit thickness has no oxidation resistance. This threshold falls as the deposition temperature is lowered. 3-nm-thick silicon nitride deposited at 600°C has sufficient oxidation resistance For wet oxidation at 850°C, while 5 nm film deposited at 750°C has no oxidation resistance. The electrical characteristics also improve as the deposition temperature is lowered. 6-nm-thick silicon nitride deposited at 600°C shows a TDDB lifetime that is about two orders longer than that of 6-nm-thick silicon nitride deposited at 700°C. It was also found that the silicon nitride transition layer which is deposited at the initial stage of deposition influences the oxidation resistance and electrical characteristics of thin silicon nitride. It was concluded that lowering the deposition temperature reduces the influence of the transition layer and improves the oxidation resistance and electrical characteristics of thin silicon nitride View full abstract»

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  • Design model and guidelines for n-well guard ring in epitaxial CMOS

    Page(s): 1806 - 1810
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    This work reports the development of design model for n-well guard rings in a CMOS process utilizing a low-doped epitaxial layer on a highly doped substrate. The validity of the model has been judged by a wide range of experimental data measured from the fabricated n-well guard ring structures with guard ring width as parameter. From the model developed, guidelines have been drawn to minimize the guard ring width while critically suppressing the amount of electrons escaping from the guard ring View full abstract»

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  • Effect of anode material on high-field-induced hole current in SiO 2 layer of metal-oxide-semiconductor field-effect transistor

    Page(s): 1819 - 1823
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    The effects of three anode materials: polysilicon (semiconductor), aluminium and gold (metals) on hole currents in oxide layers of MOSFET's are presented for both thin (19 nm) and the thick (78 nm) oxide layers. Similar anode material effects were observed in both the thin and the thick oxide layers. The results suggest that anode hole generation plays the same role for both the thin and the thick oxide layers in our experiment. The larger the anode electron barrier height, the larger the hole current generation efficiency. The observable anode material effect decreases with increase of oxide electric field. When the oxide electric field is larger than 10 MV/cm, the observable anode material effect disappears. Our results show that the anode hole generation is the dominant mechanism on both the thin and thick oxide layers for oxide electric fields smaller than 10 MV/cm. For oxide electric fields larger than 10 MV/cm, further analysis is needed to identify the dominant mechanism of high-field-induced oxide hole currents View full abstract»

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  • Characteristics of high mobility polysilicon thin-film transistors using very thin sputter-deposited SiO2 films

    Page(s): 1882 - 1885
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    Polysilicon thin-film transistors with various gate oxide thicknesses ranging from 94 to 7 nm using sputter-deposited SiO2 films were fabricated and their electrical characteristics were studied to explore the possibilities of enhancing the TFT characteristics by scaling down the gate oxide thickness. It was found that the threshold voltage and the subthreshold slope decrease linearly as the gate oxide thickness is reduced while the field effect mobilities stay constant. The breakdown electric field of the gate oxide increases as the gate oxide thickness decreases and is over 10 MV/cm when the thickness is less than 20 nm. The polysilicon TFT with the 7-nm gate oxide, the thinnest in this work, showed excellent characteristics: threshold voltage of 0.44 V, subthreshold slope of 110 mV/dec, field effect mobility of 97 cm2/Vs View full abstract»

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  • 0.3-μm mixed analog/digital CMOS technology for low-voltage operation

    Page(s): 1837 - 1842
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    A 0.3-μm mixed analog/digital CMOS technology for low-voltage operation has been demonstrated, including a new MOSFET structure with laterally doped buried layer (LDB) and a double-polysilicon capacitor with low voltage coefficient. The LDB-structure MOSFET provides constant threshold voltage which is independent of channel length, high current drivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the top polysilicon plate and a Si3N4 capacitor-insulator, despite the insulator thickness being scaled down to oxide-equivalent 20 nm View full abstract»

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  • Transport characteristics of a symmetrically extended bipolar transistor

    Page(s): 1691 - 1697
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    This work deals with a novel bipolar transistor structure consisting of a δp(B*)-δn(E)-δp(B) planar doping layer sequence embedded between two heavily doped n+ collector layers C* and C. Currents flowing in such a n+δpδnδpn+ structure are investigated under symmetrical bias conditions (VEB=VEB *, VBC=VB*C*). At VEB>0 (forward bias), electrons, injected from the E layer over the B(B*) barrier, are collected in the C(C*) layer whereas holes, injected from B and B* over the E barrier, are collected in the respective counter-layer B* and B. In this structure, at VBC=0, the difference between the total current emitted from E and the current collected in C and C* equals the electron-hole recombination current between E and B (E and B*). Accordingly, the current gain depends linearly on the recombination lifetime in the E-B(E-B*) region. At reasonable lifetimes (τ=1 μs) appreciable current gain values are obtained even at high B(B*) doping levels View full abstract»

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  • Two-dimensional energy-dependent models for the simulation of substrate current in submicron MOSFET's

    Page(s): 1784 - 1795
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    Two-dimensional energy-dependent substrate current models are described for NMOS and PMOS devices that have been developed using a multi-contour approach. The new models offer a significant improvement in the calculation of substrate current due to a more accurate calculation of the average energy as compared to the local-field model. The models are implemented in a post-processing manner by applying a one-dimensional energy conservation equation to each of many current contours in order to generate a two-dimensional representation of average energy and impact ionization rate, that is then integrated to calculate the substrate current. The new models have been compared to substrate current characteristics of a variety of NMOS and PMOS devices for a wide range of bias conditions and channel lengths, and very good agreement has been obtained with a single set of model parameters. An additional significance of this work is the enhancement of the standard multi-contour model by an energy-sink term that results in an improved prediction of the impact ionization process in PMOSFET's View full abstract»

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  • Kink effect related to the self-side-gating effect in GaAs MESFET's

    Page(s): 1873 - 1875
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    A kink effect, an abrupt increase in drain current at high drain voltages, was observed in GaAs MESFET's with an Al0.2Ga0.8As/GaAs heterostructure buffer layer. In these MESFET's, impact ionization occurs at the drain side along the channel current path at high drain voltages. On the other hand, a side-gating effect occurs when a negative voltage applied to the gate pad of the MESFET (self-side-gating effect). From measurements of the substrate potential, we conclude that hole accumulation generated by the impact ionization at the channel-side GaAs/Al0.2Ga0.8 As interface cancels the drain current reduction that arises from the self-side-gating effect. This gives rise to the kink effect we observe View full abstract»

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  • A micromachined ultra-thin-film gas detector

    Page(s): 1770 - 1777
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    This paper reports a second-generation gas detector developed for eventual use in a multi-element gas analyzer. The detector utilizes an ultra-thin metal sensing film supported on a selectively micromachined dielectric window, although the basic structure is also suitable for use with more conventional sensing films. A 5 μm-thick boron-diffused silicon heater under the window permits the window temperature to be varied between ambient and over 1200°C with heating efficiencies in air and in vacuum of 6°C/mW and 20°C/mW, respectively. The total window area is 1 mm2, with an active sensing area of 0.12 mm 2. The circuit simulator SPICE is used to optimize the coupled thermal and electrical characteristics of the window simultaneously, resulting in a simulated temperature uniformity over the sensing area of better than ±0.5%. Two boron-diffused silicon resistors having TCR's of 1800 ppm/°C are interleaved with the heater to allow the average temperature over the active area to be determined to within about ±0.1°C. The detectors are realized using a six-mask process in a die size of 2.8 mm×2.8 mm. A subset of the same process is also used to produce wafer-level shadow masks to permit the detectors to be used with any sensing films capable of being vacuum deposited View full abstract»

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  • Highly doped InGaP/InGaAs/GaAs pseudomorphic HEMT's with 0.35 μm gates

    Page(s): 1742 - 1746
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    We fabricated 0.35-μm gate-length pseudomorphic HEMT DCFL circuits using a highly doped thin InGaP layer as the electron supply layer. The InGaP/InGaAs/GaAs pseudomorphic HEMT grown by MOVPE is suitable for short gate-length devices with a low supply voltage since it does not show short channel effects even for gate length down to 0.35 μm. We obtained a K value of 555 mS/Vmm and a transconductance gm of 380 mS/mm for an InGaP layer 18.5 nm thick. Fabricated 51-stage ring oscillators show the basic propagation delay of 11 ps and the power-delay product of 7.3 fJ at supply voltage of VDD of 1 V, and 13.8 ps and 3.2 fJ at VDD of 0.6 V for gates 10 μm wide View full abstract»

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  • Drastic reduction of gate leakage in InAlAs/InGaAs HEMT's using a pseudomorphic InAlAs hole barrier layer

    Page(s): 1685 - 1690
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    Impact ionization in the channel of InAlAs/InGaAs HEMT's was shown to be a reason for excess gate leakage current. Hot electrons in the high field region of the channel under the gate generate electron-hole pairs. The generated holes can reach the gate (gate leakage) as well as the source, the electrons flow to the drain (kink effect). The number of holes reaching the gate strongly depends on the valence band discontinuity. In order to increase this valence band discontinuity a thin pseudomorphic InAlAs layer with high Al-content was inserted in the spacer of an InAlAs/InGaAs HEMT. The efficiency of this hole barrier was measured by photocurrent and DC measurements, while its influence on transport characteristics was measured by Hall and RF measurements. A reduction of gate leakage by a factor of 200 is demonstrated View full abstract»

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  • Electroluminescence characteristics and current-conduction mechanism of a-SiC:H p-i-n thin-film light-emitting diodes with barrier layer inserted at p-i interface

    Page(s): 1761 - 1769
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    In order to improve the electroluminescence (EL) characteristics of the hydrogenated amorphous silicon carbide (a-SiC:H) p-i-n thin-film light-emitting diode (TFLED), a barrier layer (BL) was inserted at its p-i interface to enhance the hole injection efficiency under forward-bias operation. The a-SiC:H TFLED's with various optical gaps of BL had been fabricated and characterized. In addition, a composition-graded n+-layer was used to reduce its series and contact resistances to the Al electrode and hence the EL threshold voltage (Vth) of an a-SiC:H BL TFLED. The highest obtainable brightness of an a-SiC:H BL TFLED was 342 cd/m2 at an injection current density of 600 mA/cm2 and the lowest EL V th achievable was 6.0 V. The current-conduction mechanism of an a-SiC:H BL TFLED had also been investigated. Within the lower applied-bias region, it showed an ohmic current, while within the higher applied-bias region, a space-charge-limited current (SCLC) was observed View full abstract»

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  • Modeling of oxide breakdown from gate charging during resist ashing

    Page(s): 1848 - 1855
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    Plasma damage was observed after exposing an antenna capacitor structure to an O2 plasma in a single wafer resist asher. The observed early breakdown is well modeled by surface charging caused by plasma nonuniformity. Here, the plasma nonuniformity was induced by gas flow and electrode configuration. The present results agree well with our previous results where magnetic field leads to a nonuniform plasma. In this model, nonuniformity leads to a local imbalance of ion and electron currents which charge up the gate surface and degrade the gate oxide. Using SPICE, a circuit model for the test structure and plasma measurements, the Fowler-Nordheim current through the thin oxide regions at different points on the wafer was calculated and found to agree well with the observed damage. The important implication of this work on oxide reliability is that the modeling gives a clear picture to this breakdown mechanism. The charging model can also be applied to any ashing process in any nonuniform plasma. Moreover, this model provides a physical basis for design rules of device structures for the fabrication of reliable gate oxides in submicron MOS technology View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology