# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 19 of 19

Publication Year: 2016, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Publication Year: 2016, Page(s): C2
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• ### 0.5-V 70-nW Rail-to-Rail Operational Amplifier Using a Cross-Coupled Output Stage

Publication Year: 2016, Page(s):1009 - 1013
Cited by:  Papers (4)
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We develop and fabricate a 0.5-V rail-to-rail operational amplifier (op-amp) with ultralow-power operation in a 0.18-μm standard complementary metal-oxide-semiconductor process. The op-amp has a two-stage structure that comprises a complementary input stage and a novel cross-coupled output stage. The cross-coupled output stage increases the transconductances of the metal-oxide-semiconductor... View full abstract»

• ### A Fast Switching Current Regulator Using Slewing Time Reduction Method for High Dimming Ratio of LED Backlight Drivers

Publication Year: 2016, Page(s):1014 - 1018
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This brief proposes a fast switching current regulator to achieve a high dimming ratio of the light-emitting diode (LED) backlight drivers. The proposed current regulator employs the slewing time reduction method to enhance the dimming ratio by decreasing the rising time of the LED forward current. A six-channel LED backlight driver was fabricated using a 0.35-μm bipolar-CMOS-DMOS process t... View full abstract»

• ### A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration

Publication Year: 2016, Page(s):1019 - 1023
Cited by:  Papers (2)
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This brief presents a two-dimensional (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated ring oscillators (GROs) in the X/Y Vernier branches. The already small Vernier quantization noise (~10.6 ps) is improved by the first-order noise shaping of the GRO. Moreover, since all the delay differences between the X and Y phases can be used (rather than only the diagonal line of t... View full abstract»

• ### A Fully Integrated RF CMOS Front-End IC for Connectivity Applications

Publication Year: 2016, Page(s):1024 - 1028
Cited by:  Papers (2)
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A fully integrated RF CMOS front-end (FE) IC (FEIC), which is fabricated with a 0.13-μm bulk RF CMOS process for wireless local area network/Bluetooth (WLAN/BT) applications, is presented. The proposed FEIC includes a dual-mode power amplifier (PA), integrated switches, and a shared low-noise amplifier (LNA) without external matching networks. The proposed compact reconfigurable matching ne... View full abstract»

• ### Simplified Logic for Tree-Structure Segmented DEM Encoders

Publication Year: 2016, Page(s):1029 - 1033
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Segmented dynamic element matching (DEM) encoders can be used in high-resolution digital-to-analog converters (DACs) to reduce nonlinear distortion that would otherwise arise from component mismatches while avoiding the high circuit complexity of non-segmented DEM encoders. This paper presents tree-structure segmented DEM encoders that have several advantages over prior segmented DEM encoders: the... View full abstract»

• ### 20-Gb/s 5-$text{V}_{mathrm{PP}}$ and 25-Gb/s 3.8-$text{V}_{mathrm{PP}}$ Area-Efficient Modulator Drivers in 65-nm CMOS

Publication Year: 2016, Page(s):1034 - 1038
Cited by:  Papers (1)
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This brief presents two area-efficient drivers for a 50-Ω terminated optical modulator. Driver 1 adopts a double cascode with dynamic biasing that enables sufficient high-speed operation owing to the high transition frequency of the thinoxide transistor. Therefore, it does not require area-consuming additional peaking inductors. A custom-designed shared inductor is used in Driver 2 for band... View full abstract»

• ### Design Tradeoffs and Predistortion of Digital Cartesian RF-Power-DAC Transmitters

Publication Year: 2016, Page(s):1039 - 1043
Cited by:  Papers (3)
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Digital RF transmitter architectures offer several advantages over conventional analog transmitters, including reduced area, reconfigurability, compatibility with scaling, and the ability to use highly efficient switching-class power amplifiers (PAs). However, the nonlinear transfer functions from the switch conductance to the output RF amplitude and phase of these switching class PAs and the inhe... View full abstract»

• ### Bandwidth Compensation Technique for Digital PLL

Publication Year: 2016, Page(s):1044 - 1048
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This brief presents a technique for compensating the bandwidth variation of digital phase-locked loops (PLLs) arising due to process, voltage and temperature (PVT) variation induced changes in loop parameters. For a digital PLL with a bang-bang phase detector, the bandwidth also depends on the phase noise level present at the input of the phase detector. The presented technique also compensates fo... View full abstract»

• ### A Mostly Digital PWM-Based $DeltaSigma$ ADC With an Inherently Matched Multibit Quantizer/DAC

Publication Year: 2016, Page(s):1049 - 1053
Cited by:  Papers (1)
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A mostly digital pulsewidth-modulator-based delta-sigma (ΔΣ) analog-to-digital converter is proposed. This system takes advantage of the duration of pulses, rather than voltage or current, as the analog operand used in its closed-loop operation. Therefore, circuits that process the pulses are digital in nature and improve with scaling. Furthermore, the architecture allows inherently ... View full abstract»

• ### A Compact Tunable Power Divider With Wide Tuning Frequency Range and Good Reconfigurable Responses

Publication Year: 2016, Page(s):1054 - 1058
Cited by:  Papers (1)
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A compact tunable power divider is proposed in this brief. The power divider can achieve a wide frequency tuning range and good matching and isolation performances. Theoretical equations for the characteristic impedance and the electrical length of the power divider are derived. For demonstration, a prototype working at 1.5 GHz as the center frequency is designed and fabricated. The measured resul... View full abstract»

• ### Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM

Publication Year: 2016, Page(s):1059 - 1063
Cited by:  Papers (1)
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A pMOS transistor with a switch is used for two purposes in a differential bitline: precharging and preamplifying during a read operation. These functions are realized by alternately changing the connection of the drain of the switching pMOS according to the operating mode. By using the same pMOS for precharging and preamplifying, the variability of a sense amplifier can be tracked, which can effe... View full abstract»

• ### Design Techniques for a 30-ns Access Time 1.5-V 200-KB Embedded EEPROM Memory

Publication Year: 2016, Page(s):1064 - 1068
Cited by:  Papers (1)
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A 200-KB embedded electrically erasable programmable READ-only memory (EEPROM), which operates with a single 1.5-V power supply voltage based on an HHGRACE (Shanghai Huahong Grace Semiconductor Manufacturing Corporation) 90-nm EEPROM process, is developed. In this brief, several key design techniques are presented. An improved bit cell with a larger current sensing window is adopted in the split-s... View full abstract»

• ### ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing

Publication Year: 2016, Page(s):1069 - 1073
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The reliability of the synchronous circuits is a critical issue due to the continuous scaling of the fabrication technology. Process, voltage, and temperature (PVT) variations increase the probability of violating the timing constraints. Different techniques are used to tolerate the variability and relax the timing of the circuits. Error recovery system using taps (ERSUT) is introduced in this bri... View full abstract»

• ### GPIO-Based Robust Control of Nonlinear Uncertain Systems Under Time-Varying Disturbance With Application to DC–DC Converter

Publication Year: 2016, Page(s):1074 - 1078
Cited by:  Papers (3)
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This brief considers the robust output-feedback control problem of a class of nonlinear uncertain systems subject to time-varying disturbances. For this purpose, a generalized proportional-integral observer (GPIO) together with a feedback domination approach is utilized for disturbance compensation and nonlinear uncertainty suppression. It is shown that the proposed control method can dominate the... View full abstract»

• ### Sparse Distributed Estimation via Heterogeneous Diffusion Adaptive Networks

Publication Year: 2016, Page(s):1079 - 1083
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Recently, diffusion networks have been proposed to identify sparse linear systems which employ sparsity-aware algorithms like the zero-attracting LMS (ZA-LMS) at each node to exploit sparsity. In this brief, we show that the same optimum performance as reached by the aforementioned networks can also be achieved by a “heterogeneous” network with only a fraction of the nodes deploying ... View full abstract»

• ### Wideband Compensation of RF Vector Multiplier for RF Predistortion Systems

Publication Year: 2016, Page(s):1084 - 1088
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This brief presents a wideband compensation method that addresses the hardware imperfections exhibited in an RF vector multiplier (RF-VM) used for RF predistortion systems. A wideband RF-VM model is first developed to embed the various sources of imperfections in an RF-VM. A compensation method is then presented, followed by a newly proposed identification algorithm to determine the parameters of ... View full abstract»

• ### IEEE Circuits and Systems Society Information

Publication Year: 2016, Page(s): C3
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## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org