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Consumer Electronics, IEEE Transactions on

Issue 3 • Date Aug 1994

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Displaying Results 1 - 25 of 78
  • Block delta modulation for compression of surveillance video signals

    Publication Year: 1994 , Page(s): 458 - 465
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    This paper describes a new methodology for coding the surveillance video signals by means of delta modulation and statistical estimations. This codec is simpler than the CCITT MPEG or H.261 Recommendation and is more suitable for the usage in close-circuit TV (CCTV) systems. With the statistical characteristics resulting from the sequence of images in surveillance systems, the proposed compression scheme is based on 8×8 pixel blocks of temporal differences. According to a modal selection of blocks, each block is further coded in different modes: the BDM (block delta modulation), ABDM (adaptive block delta modulation), DCT and ZERO modes. From the simulation results, a compression ratio of 1:47 and a PSNR of 37 dB are obtained when the above hybrid coder is used to encode the lady and walking men sequences View full abstract»

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  • A remote electronic object emulation system for home bus applications

    Publication Year: 1994 , Page(s): 405 - 410
    Cited by:  Papers (3)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    The design and implementation of a hardware emulation system for CEBus Objects is described. The emulator is accessed remotely from a PC-based GUI. It may be easily programmed to combine several CAL objects to emulate common CEBus devices View full abstract»

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  • An advanced multi-standard TV video/sound IF

    Publication Year: 1994 , Page(s): 290 - 298
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    This paper describes a circuit which performs the functions of IF amplification, AGC, AFT, and demodulation of a TV video and sound IF signal for PAL, NTSC, SECAM, and AM D2MAC View full abstract»

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  • MPEG2 video codec using image compression DSP

    Publication Year: 1994 , Page(s): 466 - 472
    Cited by:  Papers (17)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    An MPEG2 digital video codec was developed. We estimated the amount of calculation power requested for MPEG2 and designed the architecture of the codec. In order to make the codec compact, we developed an integrated image compression digital signal processor (called VDSP2). The VDSP2 integrates four different types of processors in the architecture that allows them to operate in parallel. The device is capable of both encoding and decoding the MPEG2-based algorithm by changing programs on the same chip. We also developed new dedicated hardware for motion estimation, which consists of two-pixel precision estimation and full and half pixel precision estimation. The codec is capable of processing MPEG2 main profile at main level in real-time at broadcast resolutions View full abstract»

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  • Strategies for multi-rate recording for a consumer digital VCR

    Publication Year: 1994 , Page(s): 263 - 268
    Cited by:  Papers (1)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    This paper explores strategies for varying data rates while maintaining tape data density in low-cost digital VCRs by using sequential head-switching techniques View full abstract»

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  • Parallel implementation of transform-based DCT filter-bank for video communications

    Publication Year: 1994 , Page(s): 473 - 475
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    This paper proposes a new filter bank structure based on the discrete cosine transform (DCT) and inverse DCT (IDCT) using modified autoregressive filter realization for real-time applications. The number of multipliers required in the synthesis bank is only N-1, which is the minimum number of multipliers for the IDCT compared to previous architectures. The VLSI implementations of the filter modules show that it can achieve 116 Mb/s and 540 Mb/s data rate under 2 μm and 0.8 μm CMOS SPDM technology View full abstract»

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  • A low cost, monolithic, color picture-in-picture device

    Publication Year: 1994 , Page(s): 306 - 316
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB)  

    A complete low cost, bus controlled, NTSC color picture-in-picture device using 0.8 μm BiCMOS technology is described. A total system integration has been achieved that includes a field memory plus digital and analog video signal processing View full abstract»

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  • Menu driven user interface for home system

    Publication Year: 1994 , Page(s): 587 - 597
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1296 KB)  

    A new on-screen menu based user interface has been developed for a CEBus home system. Menus are generated in a system controller and distributed via CEBus network to TVs. This system provides virtual control panels throughout the house View full abstract»

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  • CAM-based VLSI architectures for dynamic Huffman coding

    Publication Year: 1994 , Page(s): 282 - 289
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    The dynamic Huffman coding is a data compression technique, and famous for its flexibility. However, it has not been available for real-time applications because the adaption process is complex. In this paper, we proposed the architectures for dynamic Huffman coding. Both of the encoder and decoder are constructed by using the CAM-based memory modules. These memory modules parallelly perform the adaption, process so that the coding can be efficiently executed. The encoder with the code table containing 32 symbols has been implemented. The simulation results show that the encoder can yield a input throughput of 40 Mbps operating at 40 MHz with 50% compression ratio View full abstract»

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  • 1994 International Conference on Consumer Electronics

    Publication Year: 1994
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1696 KB)  

    The following topics were dealt with: audio technology; emerging technologies; ATV standards conversion; digital video cassette recorders; signal processing IC technology; interactive television; ATV image coding and applications; consumer video recording; multimedia systems; user interfaces; image compression; electronic imaging; legislation; TV sound and radio; residential automation; camcorders; digital television and ATV transmission; ghost cancellation; ATV ICs; scan conversion and geometry correction; digital audio signal processing View full abstract»

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  • Data selection strategies for digital VCR long play mode

    Publication Year: 1994 , Page(s): 269 - 273
    Cited by:  Papers (2)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    This paper provides methods for implementing a long play mode on compressed digital VCRs, similar to 4 and 6 hour modes on analog VCRs. Data selection strategies for forming a reduced rate compliant bitstream are described View full abstract»

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  • Development of DARC decoding LSI for high-speed FM subcarrier system

    Publication Year: 1994 , Page(s): 570 - 579
    Cited by:  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (876 KB)  

    Expectations have been running high for a new generation of FM broadcasting systems targeted at mobile FM reception, notably in cars. The DARC (data radio channel) is an FM multiplex broadcasting system designed to address these expectations. When compared with the RDS (radio data system) and the RBDS (radio broadcast data system) which have already gone into service in Europe and the United States, the DARC system features an over-tenfold transmission capacity. Other features include the L-MSK (level-controlled minimum shift keying) modulation system, the incorporation of powerful error-correction code, a wide service area, and so forth. In developing LSIs, we have set the following three major goals: ease of incorporation into FM receivers, elimination of adjustments, and minimization of add-on components View full abstract»

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  • A highly integrated scanning rate converter for IQTV

    Publication Year: 1994 , Page(s): 727 - 734
    Cited by:  Papers (4)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    The paper describes the multipurpose scanning rate converter (MSRC) IC, which improves TV image quality applying advanced scanning rate and format conversion techniques. The device has been designed to be inserted in an IQTV receiver to remove interlaced scan-related artifacts. The MSRC has been integrated using the 0.7 um CMOS technology, following a mixed custom/semicustom design approach View full abstract»

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  • An individually addressable TV receiver with interactive channel guide display, VCR, and cable box control

    Publication Year: 1994 , Page(s): 317 - 328
    Cited by:  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB)  

    In this system a high performance TV receiver has been adapted to automatically detect and interface with a daughter module that processes, stores, and maintains data pertaining to TV programs up to one week in the future. The TV receiver is provided by Zenith Electronics. The program data is provided by StarSight Telecast Inc View full abstract»

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  • A revised conformance test method of layer 3 of HBS standard

    Publication Year: 1994 , Page(s): 598 - 604
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    An important problem that must be solved as home automation (HA) gains in popularity is interconnection of HA devices developed by different vendors. A method of solution is to test conformance of HA devices to standard specifications. The authors therefore have been researching a conformance test method for layers 1, 2, and 3 of the HBS (Home Bus System) standard of Japan (R. Hamabe et al., 1988). A test coordination procedure is proposed to create an appropriate and economical implementation under test (IUT). A few examples of a test method are given concerning a system common command (SCC) and a communication sequence (CS) of the HBS standard. It is shown that the conformance test program can he developed as a simple structured programming by paying attention to a test sequence community. Moreover the standard software functions of the system under test (SUT) are indicated View full abstract»

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  • Customer network with a highly reliable design method using short-wavelength electro-optical devices and optical fibers

    Publication Year: 1994 , Page(s): 580 - 586
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    The paper describes the construction of a customer network and its highly reliable design method that uses short-wavelength electro-optical devices and plastic optical fibers. The network is well suited for application to apartment houses View full abstract»

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  • Motion adaptive deinterlacer for DMD (digital micromirror device) based digital television

    Publication Year: 1994 , Page(s): 735 - 742
    Cited by:  Papers (8)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB)  

    The paper describes a deinterlacer developed for use in display systems based on the DMD (digital micromirror device), a new digital display technology. The deinterlace algorithm performs motion adaptive interpolation, using median filtered interframe differences to generate the motion signal. The interpolation process is edge adaptive, using five different edge orientations computed from the original interlace picture. Progressive scan-rate individual bit plane level digital data is then used to drive the DMD display using a pulse width modulation (PWM) technique. Real-time implementation is realized using the scan-line video processor (SVP) View full abstract»

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  • SD-VCR: a high data rate versatile recorder

    Publication Year: 1994 , Page(s): 243 - 249
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    A 1024 track stationary head digital recorder has been developed. Although using conventional half inch magnetic tape, this recorder uses new developed components for writing and reading such high number of parallel tracks. We show how this technology is a breakthrough towards higher density, higher data rate and simpler transport mechanism View full abstract»

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  • A 2.9 megabit field memory especially suitable for PALplus applications

    Publication Year: 1994 , Page(s): 718 - 726
    Cited by:  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (708 KB)  

    Today's television has reached a high state of picture quality, and further major improvements are limited by the restrictions of the transmission standard. However, as IC technology advances, means have become available to eliminate or reduce many of the effects which still impair a perfect picture rendition. Among these effects are large-area flicker, line-flicker, cross talk between luminance and chrominance, and noise. Most of the TV makers working in that application area, normally referred to as IDTV (improved definition TV), use dedicated ASM called field memories (FMEMs), to store in an appropriate digital format the picture received by the TV set, and to apply to it DSP concepts, in order to improve the above mentioned effects. A novel architecture of a 2.9 Mbit field memory that is emerging as a European Industry Standard in IDTV applications, is described. Further evolution of the device specially suitable for PALplus applications is also described View full abstract»

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  • Combined TV format control and sampling rate conversion IC

    Publication Year: 1994 , Page(s): 711 - 717
    Cited by:  Papers (3)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    A CMOS IC, employing digital interpolation techniques for raster mapping of video signals and including analogue signal processing functions is described. Horizontal format control, sample rate conversion of non line-locked sampled sources and decoupling of deflection signals with respect to the input signal is performed. Both digital and analogue outputs are available from the IC View full abstract»

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  • A high performance video server for karaoke systems

    Publication Year: 1994 , Page(s): 329 - 336
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    A high performance and low cost video server architecture is proposed for karaoke systems which can store more than 200 Gbytes of video and support up to 30 concurrent users simultaneously. Moreover, a novel caching strategy, called head caching, is proposed which can significantly reduce the initial delay. With this strategy, the initial delay can be dramatically reduced without increasing the cache size. Besides, using head caching scheme, the proposed system can act as a general video server which can support fast-forward, rewind, and dynamic panning controls View full abstract»

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  • A high speed bit stream generator for HDTV

    Publication Year: 1994 , Page(s): 549 - 556
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (848 KB)  

    In developing high speed digital video decoder systems such as MPEG I, II, multimedia decoder or high-definition TV (HDTV), it is essential to have a real time data stream generation apparatus. In this paper, a real time bit stream generator using conventional SCSI-II type hard disc is proposed and implemented, and its effectiveness is verified in developing the prototype HDTV decoder system. The design concept and implementation are described. The bit stream generator and HDTV decoder had been successfully demonstrated View full abstract»

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  • A PALplus compatible HDTV encoder system

    Publication Year: 1994 , Page(s): 207 - 215
    Cited by:  Papers (3)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1024 KB)  

    The paper presents a new implementation for realising PALplus signals from high-definition television (HDTV) transmissions. A proposed encoder design is introduced, which decomposes the HDTV input into two separate channels, the first of which subsamples the input signal to produce the standard resolution TV signal, and the second derives a digitally compressed residual component. The problems of non-uniform line structure due to the decimation of an interlaced signal are addressed, as are the visible distortions caused by aliasing and cross-talk effects, with appropriate solutions presented. Finally the important issues of colour enhancement and the composition of the compatible signal are briefly discussed View full abstract»

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  • A flexible scanning system for multi-format video cameras

    Publication Year: 1994 , Page(s): 605 - 609
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    A flexible pulse generating system for imager scanning was successfully developed. This system is suitable for digital processing video cameras which are controlled by a microcomputer and provides various image formats which are not only NTSC/PAL formats but also some suitable formats for video capture in multimedia use View full abstract»

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  • A small size deck mechanism and recording technology for digital VCRs

    Publication Year: 1994 , Page(s): 363 - 371
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    We have developed a small size mechanism for home-use digital VCRs. A new tape transport system suitable for thin metal evaporated (ME) tape has been developed. As a result, a track linearity within 3 μm and a CN ratio of approximately 50 dB (RBW:30 kHz) have been realized View full abstract»

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Aims & Scope

The main focus for the IEEE Transactions on Consumer Electronics is the engineering and research aspects of the theory, design, construction, manufacture or end use of mass market electronics, systems, software and services for consumers.

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Simon Sherratt, IEEE Fellow
Professor of Consumer Electronics
School of Systems Engineering
The University of Reading
Reading, Berkshire RG6 6AY  U.K.
r.s.sherratt@reading.ac.uk; sherratt@ieee.org
Phone:+44 (0) 118 3788588