By Topic

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 10 • Date Oct 1994

Filter Results

Displaying Results 1 - 11 of 11
  • Time-domain macromodels for VLSI interconnect analysis

    Page(s): 1257 - 1270
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (960 KB)  

    This paper presents a method of obtaining time-domain macromodels of VLSI interconnection networks for circuit simulation. The goal of this work is to include interconnect parasitics in a circuit simulation as efficiently as possible, without significantly compromising accuracy. Stability issues and enhancements to incorporate transmission line interconnects are also discussed. A unified circuit simulation framework, incorporating different classes of interconnects and based on the proposed macromodels, is described. The simplicity and generality of the macromodels is demonstrated through examples employing RC- and RLC-interconnects View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The implementation of physical boundary conditions in the Monte Carlo simulation of electron devices

    Page(s): 1241 - 1246
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    This paper investigates the problem of specifying and implementing physical boundary conditions for the Monte Carlo (MC) simulation of electron dynamics in semiconductor devices. The goal of this work is to establish an accurate and efficient ohmic boundary condition scheme for use in characterizing realistic device structures. In this work, three distinct physical models for specifying the boundary electrons at the ideal ohmic contacts of an N+-N-N+ GaAs Ballistic diode structure are investigated. This study demonstrates that a displaced Maxwellian scheme, which allows for an electron ensemble with momentum space displacement and random spread, presents definite computational advantages when one is interested in resolving asymmetries in the electron distribution function throughout the semiconductor device structure View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An object-oriented approach to device simulation-FLOODS

    Page(s): 1235 - 1240
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    C++ and object-oriented programming techniques are becoming popular for their modularity, ease of use, and simplicity to maintain and enhance. This paper describes an approach used for device simulation. The object library and organization are described. Specific areas of modularity and enhancement are illustrated in both the areas of physical models and mathematics. Comparisons of both performance and ease of enhancement are made to PISCES-II View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Iterative placement improvement by network flow methods

    Page(s): 1189 - 1200
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1092 KB)  

    We describe an efficient iterative improvement procedure for row-based cell placement with special emphasis on the objective function used to model net lengths. Two new net models are introduced and we prove theoretically that the net models are accurate approximations of the widely used half perimeter of a rectangle enclosing all pins of a net. In addition, unlike the half perimeter model, our net models allow us to compute costs for assigning cells to locations independently for all cells to be placed simultaneously. This offers our algorithm an important advantage compared to other iterative improvement techniques: many cells can be placed simultaneously by formulating placement as a network flow problem. This makes our algorithm more independent from a processing sequence than standard iterative improvement techniques. Finally, we compare our method to some existing algorithms including TimberWolfSC 5.4. We ran all of the algorithms on the SIGDA Benchmark Suite. We found that our method produced solutions with up to 23% less layout area while using an order of magnitude less running time compared to TimberWolfSC 5.4 View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Numerical modeling of a micromachined thermal conductivity gas pressure sensor

    Page(s): 1247 - 1256
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (884 KB)  

    We have developed a software package that simulates the operation of a silicon micromachined CMOS thermal conductivity gas pressure gauge. The performance of actual devices was compared against the simulated operation and was found to be in good agreement. The 3-dimensional simulation was reduced to two 2-dimensional simulations to reduce complexity. The two equations resulting from steady state energy balance considerations were discretized and an iterative nonlinear Gauss-Seidel procedure applied to solve the system of equations. Temperature profiles and contours were calculated and the effect of geometric and materials modifications was demonstrated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A probabilistic timing approach to hot-carrier effect estimation

    Page(s): 1223 - 1234
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1180 KB)  

    In this paper, a new approach is presented for estimating the hot-carrier induced degradation in MOS transistors in VLSI circuits. With the decrease in feature size, many long-term reliability issues, such as HCE (Hot-Carrier Effect), TDDB (Time-Dependent Dielectric Breakdown), etc., can no longer be ignored during the design process. In this work we mainly concentrate on HCE; however, the approach can be applied to investigate other reliability issues. HCE is a long-term reliability issue that is caused by the cumulative effects of all possible inputs on the devices in the circuit over time. Existing techniques use deterministic circuit or timing simulation to estimate HCE and try to predict the age of the design by incorporating device degradation over time. As a result, all HCE simulators are too slow (especially if linked to SPICE-circuit simulators) for large circuits; and even when fast simulation techniques are used, user-specified deterministic input waveforms are needed and, hence, the results can only represent a small sample of operating conditions. In this paper, we propose a probabilistic timing approach. The advantage of probabilistic simulation is that we can explore the cumulative effects of all possible input waveform combinations in one run. The approach has been implemented in a general-purpose simulator and tested on a number of typical examples and benchmarks View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts

    Page(s): 1201 - 1222
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2012 KB)  

    Folding or topological compaction of array-based VLSI layouts is an important optimization step that is carried out after logic synthesis. In this paper, a new approach to two-dimensional multiple folding of array-based VLSI layouts is presented. From the specification of the problem a pair of intersection graphs is created. We show that any pair of interval graphs that contain the intersection graphs as spanning subgraphs corresponds to a set of feasible foldings. Next, a complete and exact characterization of the folding problem is presented. In particular, it is shown that the set of all feasible foldings associated with a given pair of interval graphs corresponds to the set of independent colorings of a pair of compatibility graphs. The compatibility graphs are derived from a pair of interval graphs that contain the intersection graphs as spanning subgraphs. Thus, minimizing the area of a layout is tantamount to finding a pair of compatibility graphs such that the product of their chromatic numbers is minimum. As important as minimizing the area of a layout is, the ability to rapidly generate compact layouts over a wide range of aspect ratios is often equally, if not more, important. The interval graph-based formulation of the folding problem permits a controlled and systematic generation of compact layouts with varying aspect ratios. Efficient and provably correct algorithms to generate compact layouts that have a given number of rows or a given number of columns within their minimum and maximum possible values are given. The basic theory and methods are extended to include I/O and other types of constraints. Finally, the results of experiments that were carried out on a large number of benchmark problems are given. These results are compared with those obtained by previously reported methods View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Architectural level test generation for microprocessors

    Page(s): 1288 - 1300
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1236 KB)  

    Hierarchically designed microprocessor-like VLSI circuits have complex data paths and embedded control machines to execute instructions. When a test pattern has to be applied to the input of an embedded module, determination of a sequence of instructions, which will apply this pattern and propagate the fault effects, is extremely difficult. After the instruction sequence is derived, to assign values at all interior lines without conflicts is also very difficult. In this paper, we propose a separation of test generation process into two phases: path analysis and value analysis. In the phase of path analysis, a new methodology for automatic assembly of a sequence of instructions is proposed to satisfy the internal test goals. In the phase of value analysis, an equation-solving algorithm is used to compute an exact value solution for all interior lines. This new ATPG methodology containing techniques for both path and value analysis forms a complete solution for a variety of microprocessor-like circuits. This new approach has been implemented and experimented on six high-level circuits. The results show that our approach is very effective in achieving complete automation for high-level test generation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Inverter models of CMOS gates for supply current and delay evaluation

    Page(s): 1271 - 1279
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    The subject of this paper is the reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits. No restrictions are applied to either the number of switching inputs or the transition times and relative delays of the input voltages. The relative positions of the switching inputs are also accounted for in the case of series-connected MOSFET's. When combined with our previously reported CMOS inverter model, the peak current is obtained in a time approximately three orders faster than HSPICE with the level-3 MOSFET model. The corresponding accuracy is around 12%. If the current waveform is required, the speed improvement is about an order less. Since the inverter model also yields the delay at no extra cost, the timing of the current waveforms can be done automatically, without recourse to a timing simulator. Although the emphasis here is on CMOS static gates, the method is applicable to dynamic logic gates as well View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Logic synthesis for field-programmable gate arrays

    Page(s): 1280 - 1287
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Recursive convolution and discrete time domain simulation of lossy coupled transmission lines

    Page(s): 1301 - 1305
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    Recursive convolution has been used in conjunction with rational function approximation to significantly improve the efficiency of the transient analysis of lossy coupled transmission lines. However, the algorithm has been mainly limited to distinct real poles. This paper presents a general algorithm for recursive convolution that includes complex conjugate pole pairs and high order real poles. These cases arise in the computation of the rational function approximations for lossy coupled transmission lines View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu