# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 17 of 17

Publication Year: 2016, Page(s):C1 - C4
| |PDF (410 KB)
• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2016, Page(s): C2
| |PDF (76 KB)
• ### A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems

Publication Year: 2016, Page(s):3193 - 3207
Cited by:  Papers (1)
| |PDF (3057 KB) | HTML

Runtime attacks on memory, such as buffer overflow based stack smashing and code reuse attacks, are common in embedded systems. Control flow integrity (CFI) has been acknowledged as one promising approach to protect against such runtime attacks. However, previous CFI implementations suffer from coarse granularity (which can be circumvented by an advanced attack model) and high-performance overhead... View full abstract»

• ### Reconfigurable Systolic Array: From Architecture to Physical Design for NML

Publication Year: 2016, Page(s):3208 - 3217
Cited by:  Papers (5)
| |PDF (2823 KB) | HTML

NanoMagnet logic (NML) is among the emerging technologies that might replace CMOS in the next decades. According to its physical characteristics, to better exploit the potential of this technology-and of other similar ones-the use of parallel architectures with regular layout that avoid long interconnection signals is advised. Systolic arrays (SAs) are among these architectures, being composed of ... View full abstract»

• ### A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Publication Year: 2016, Page(s):3218 - 3231
| |PDF (2503 KB) | HTML

Ongoing advancements in 3-D manufacturing are enabling 3-D ICs to contain several processing cores, hardware accelerators, and dedicated peripherals. Most of these functional units operate with independent clock frequencies for power management reasons or simply for being hard intellectual properties. Thus, as diverse and heterogeneous circuits can be implemented on a 3-D IC, it also leads to the ... View full abstract»

• ### All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator

Publication Year: 2016, Page(s):3232 - 3242
Cited by:  Papers (2)
| |PDF (2763 KB) | HTML

In this paper, an all-digital ON-chip process sensor using a ratioed inverter-based ring oscillator is proposed. Two types of the ratioed inverter-based ring oscillators, nMOS and pMOS types, are proposed to sense process variation. The nMOS (pMOS)-type ring oscillator is designed to improve its sensitivity to the process variation in the nMOS (pMOS) transistors using the ratioed inverter that con... View full abstract»

• ### EMBIRA: An Accelerator for Model-Based Iterative Reconstruction

Publication Year: 2016, Page(s):3243 - 3256
| |PDF (6380 KB) | HTML

Tomographic reconstruction, which involves computing a 3-D volume from its 2-D projections, is an important problem in imaging with wide-ranging applications, including medical scanners, electron microscopy, nondestructive testing, and transportation security. Model-based iterative reconstruction (MBIR) is a popular approach to 3-D reconstruction that has demonstrated the state-of-the-art reconstr... View full abstract»

• ### Low-Latency ECDSA Signature Verification—A Road Toward Safer Traffic

Publication Year: 2016, Page(s):3257 - 3267
Cited by:  Papers (2)
| |PDF (3571 KB) | HTML

Car-to-car and car-to-infrastructure messages exchanged in intelligent transportation systems can reach reception rates over 1000 messages per second. As these messages contain elliptic curve digital signature algorithm (ECDSA) signatures, this puts a very heavy load onto the verification hardware. In fact, the load is so high that, currently, it can only be achieved by implementations running on ... View full abstract»

• ### Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology

Publication Year: 2016, Page(s):3268 - 3281
Cited by:  Papers (2)
| |PDF (3816 KB) | HTML

In this paper, a number of novel 1-bit full adder cells using carbon nanotube field-effect transistor devices are presented. First of all, some two-input XOR/XNOR circuits are proposed, and then, they are employed to form 1-bit full adders. Totally, five full adders with driving power and one without driving power are proposed in this paper, each of which has its own merits. Simulations with regar... View full abstract»

• ### Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor

Publication Year: 2016, Page(s):3282 - 3295
Cited by:  Papers (1)
| |PDF (5653 KB) | HTML

Measuring temperature and voltage (T&V) in a current VLSI is very important in guaranteeing its reliability, because a large variation of temperature or voltage in field will reduce a delay margin and makes the chip behavior unreliable. This paper proposes a novel method of T&V measurement, which can be used for variety of applications, such as field test, online test, or hot-spot monitoring. The ... View full abstract»

• ### A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction

Publication Year: 2016, Page(s):3296 - 3309
| |PDF (2902 KB) | HTML

Scratchpad memory (SPM) is widely used in modern embedded processors to overcome the limitations of cache memory. The high vulnerability of SPM to soft errors, however, limits its usage in safety-critical applications. This paper proposes an efficient fault-tolerant scheme, called cache-assisted duplicated SPM (CADS), to protect SPM against soft errors. The main aim of CADS is to utilize cache mem... View full abstract»

• ### Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect

Publication Year: 2016, Page(s):3310 - 3322
| |PDF (5249 KB) | HTML

Three-dimensional integration is considered to be a promising technology to tackle the global interconnect scaling problem for terascale integrated circuits (ICs). Three-dimensional ICs typically employ through-silicon-vias (TSVs) to vertically connect planar circuits. Due to its immature fabrication process, several defects, such as void, misalignment, and dust contamination, may be introduced. T... View full abstract»

• ### Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver

Publication Year: 2016, Page(s):3323 - 3333
Cited by:  Papers (3)
| |PDF (6267 KB) | HTML

In this paper, a Golay-correlator window-based noise cancellation (GC-WNC) technique with frequency-domain equalizer (FDE) is proposed. The GC-WNC is a cooperative scheme in the time and frequency domains to combat the multipath effect in nonline-of-sight (NLOS) and LOS channels for orthogonal frequency-division multiplexing (OFDM) and single-carrier mode baseband inner receiver over 60-GHz enviro... View full abstract»

• ### A 24- $\mu \text{W}$ 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS

Publication Year: 2016, Page(s):3334 - 3344
Cited by:  Papers (1)
| |PDF (5843 KB) | HTML

This paper presents an energy-efficient 12-bit successive approximation (SA) register analog-to-digital converter (ADC) for high-performance sensor systems. The ADC uses a two-step decision digital-to-analog converter (DAC) switching scheme for improving the DAC linearity with small capacitor arrays. The scheme effectively eliminates the largest binary DAC middle-code transition glitch. The propos... View full abstract»

• ### Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips

Publication Year: 2016, Page(s):3345 - 3358
| |PDF (5891 KB) | HTML

Digital microfluidic biochips (DMFBs), a second-generation lab-on-chip device has developed in recent years as a feasible alternative to conventional laboratory procedure for biochemical analysis and diagnostic applications. These devices enable the precise manipulation of nanoliter volumes of biological fluids and chemical reagents within a 2-D rectangular array of electrodes. Increasing number o... View full abstract»

• ### Defragmentation for Efficient Runtime Resource Management in NoC-Based Many-Core Systems

Publication Year: 2016, Page(s):3359 - 3372
| |PDF (3221 KB) | HTML

Efficient runtime resource allocation is critical to the overall performance and energy consumption of many-core systems. A region of free cores is allocated for each newly launched application. The cores are deallocated when the corresponding applications finish execution. The frequent allocations and deallocations of the cores might leave free cores scattered (not forming a contiguous region). T... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2016, Page(s): C3
| |PDF (62 KB)

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu