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IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 65

Publication Year: 2016, Page(s):C1 - 4150
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• IEEE Transactions on Electron Devices publication information

Publication Year: 2016, Page(s): C2
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• Compact Modeling of Surface Potential, Charge, and Current in Nanoscale Transistors Under Quasi-Ballistic Regime

Publication Year: 2016, Page(s):4151 - 4159
Cited by:  Papers (1)
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In this paper, we have proposed a new analytical model for FETs working in the quasi-ballistic regime. The model is based on a calculation of the charge density along the channel which is then used to solve Poisson's equation to get the variation of the channel potential. This is then used to calculate the ballistic and drift-diffusive components of the current. The model is capable of accurately ... View full abstract»

• Modeling of the Lateral Emitter-Current Crowding Effect in SiGe HBTs

Publication Year: 2016, Page(s):4160 - 4166
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Two-section models for capturing the lateral ac emitter-current crowding effect, which is also known as the lateral nonquasi-static (NQS) effect, are presented following a consistent approach based on a model formulation for ac operating condition. Following the theoretical results, model formulations suitable for implementation in the large-signal domain are developed. The proposed two-section mo... View full abstract»

• Random Dopant Fluctuation-Induced Threshold Voltage Variation-Immune Ge FinFET With Metal–Interlayer–Semiconductor Source/Drain

Publication Year: 2016, Page(s):4167 - 4172
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The impact of process-induced random dopant fluctuation (RDF)-induced threshold voltage (Vth) variation on the performance of 7-nm n-type germanium (Ge) FinFETs with and without a metal-interlayer-semiconductor (MIS) source/drain (S/D) structure is investigated using 3-D TCAD simulations. In order to reduce the RDF-induced Vth variation, an MIS S/D structure with a heavily doped n-type ... View full abstract»

• Line Tunneling Dominating Charge Transport in SiGe/Si Heterostructure TFETs

Publication Year: 2016, Page(s):4173 - 4178
Cited by:  Papers (1)
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This paper provides an experimental proof that both the ON-current ION and the subthreshold swing SS of Si(Ge)-based tunneling FETs (TFETs) drastically benefit from device architectures promoting line tunneling aligned with the gate electrical field. A novel SiGe/Si heterostructure TFET is fabricated, making use of a selective and self-adjusted silicidation, thus enlarging the area for band-to-ban... View full abstract»

• High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

Publication Year: 2016, Page(s):4179 - 4184
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In this paper, the Pi-gate (PG) poly-Si junction-less (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width ~ 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shap... View full abstract»

• Raised Source/Drain Dopingless Junctionless Accumulation Mode FET: Design and Analysis

Publication Year: 2016, Page(s):4185 - 4190
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We design and analyze a raised source/drain dopingless junctionless accumulation mode FET (RDJAMFET) on an intrinsic silicon film using charge plasma concept. This device does not have any physical doping or junctions. Using 2-D simulations, we demonstrate that by making use of the physical design parameters, the device can achieve reduced bandto-band tunneling-induced parasitic bipolar transistor... View full abstract»

• Electron Mobility in Junctionless Ge Nanowire NFETs

Publication Year: 2016, Page(s):4191 - 4195
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The electron mobility in junctionless (JL) Ge nanowire nFETs with the (110) channel direction is calculated and compared with experimental data. The calculation of the electron mobility is based on the Kubo-Greenwood formula. The wave functions are obtained by solving the self-consistent Poisson-Schrödinger equation. Phonon scattering, surface roughness scattering, and Coulomb scattering (... View full abstract»

• Hybrid Open Drain Method and Fully Current-Based Characterization of Asymmetric Resistance Components in a Single MOSFET

Publication Year: 2016, Page(s):4196 - 4200
Cited by:  Papers (1)
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Separate extraction of source (RS) from drain resistance (RD) is important in the systematic modeling of electrical characteristics and investigation of physical mechanism related to the performance and reliability in MOSFETs and their integrated circuits. We report a hybrid open drain method (ODM), as a fully current-based characterization technique, for a comprehensive separation of asymmetric s... View full abstract»

• Charge-Based Compact Model for Bias-Dependent Variability of 1/ $f$ Noise in MOSFETs

Publication Year: 2016, Page(s):4201 - 4208
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Variability of low frequency noise (LFN) in MOSFETs is bias-dependent. Moderate-to-large-sized transistors commonly used in analog/RF applications show 1/f-like noise spectra, resulting from the superposition of random telegraph noise. Carrier number and mobility fluctuations are considered as the main causes of LFN. While their effect on the bias-dependence of LFN has been well investigated, the ... View full abstract»

• A New Device-Physics-Based Noise Margin/Logic Swing Model of Surrounding-Gate MOSFET Working on Subthreshold Logic Gate

Publication Year: 2016, Page(s):4209 - 4217
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In this paper, we present a device-physics-based noise margin (NM)/logic swing (LS) model of surrounding-gate (SRG) MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of the main dc parameters, including LS and NM for SRG MOSFET operating in low-voltage condition, is revealed. It is shown that the device parameters, su... View full abstract»

• AlGaN/GaN HEMTs on Silicon With Hybrid Schottky–Ohmic Drain for RF Applications

Publication Year: 2016, Page(s):4218 - 4225
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In this paper, the AlGaN/GaN high electron mobility transistors on a low resistivity Si substrate with the hybrid drain structure for RF applications are analyzed in detail, based on measurements, TCAD simulation, model extraction, and delay time calculation of the transistors. Owing to the E-field redistribution of the Schottky extension, both the leakage current and the breakdown voltage can be ... View full abstract»

• A Compact Model of Drain Current for GaN HEMTs Based on 2-DEG Charge Linearization

Publication Year: 2016, Page(s):4226 - 4232
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A physics-based simple and accurate compact model of drain current for GaN-based high electron mobility transistors (HEMTs) is presented. The model is developed using analytical relations for charges in the 2-D electron gas and barrier layer. For the first time, a simple charge linearization approach has been used for GaN-based HEMTs. The access regions are accurately modeled using transistors. Th... View full abstract»

• Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 1: Experimental Devices

Publication Year: 2016, Page(s):4233 - 4239
Cited by:  Papers (1)
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Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggrega... View full abstract»

• Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 2: Simulation Study of the Impact of Interface Traps

Publication Year: 2016, Page(s):4240 - 4247
Cited by:  Papers (3)
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This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET (TFET) with the same geometry as the fabricated device discussed in the first part. In addition to band-to-band tunneling, trap-assisted tunneling (TAT) at the InAs/Si and InAs/oxide interfaces was considered. A very good agreement is found between the simulation results and experimental transfer chara... View full abstract»

• Calibration of the Effective Tunneling Bandgap in GaAsSb/InGaAs for Improved TFET Performance Prediction

Publication Year: 2016, Page(s):4248 - 4254
Cited by:  Papers (2)
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The effective bandgap for heterojunction band-to-band tunneling (Eg,eff) is a crucial design parameter for a heterojunction tunneling FET (TFET). However, there is significant uncertainty on Eg,eff, especially for In0.53Ga0.47As/GaAs0.5Sb0.5. This makes the prediction of TFET performance difficult. We calibrate Eg,eff by ... View full abstract»

• RF Performance of Trigate GaN HEMTs

Publication Year: 2016, Page(s):4255 - 4261
Cited by:  Papers (2)
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The impact of the trigate GaN high electron mobility transistor (HEMT) body geometry on the device RF performance is investigated by 3-D numerical simulations. The trigate concept is a viable approach to achieve normally off operation and to suppress short-channel effects. The effect of gate length scaling on the RF behavior is studied and guidelines for design improvements are provided. Furthermo... View full abstract»

• Influence of Al/Si Codiffusion on Current Gain Deterioration in AlGaN/GaN Single Heterojunction Bipolar Transistors

Publication Year: 2016, Page(s):4262 - 4266
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AlGaN/GaN single heterojunction bipolar transistors (SHBTs) without using regrown emitter junction are demonstrated. Secondary ion mass spectroscopy analysis shows that a severe codiffusion of Al and Si exists in AlGaN/GaN heterostructures grown at 780 °C. The altered composition and doping profiles greatly degrade the common-emitter current gain of AlGaN/GaN HBTs to ≤0.8. A GaN spac... View full abstract»

• Study of Inherent Gate Coupling Nonuniformity of InAs/GaSb Vertical TFETs

Publication Year: 2016, Page(s):4267 - 4272
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An electrostatic nonuniformity in the cantilever vertical tunneling FETs intrinsically exists in the InAs/GaSb junction to InAs cantilever transition region. The effects of the coupling ratio (CR) nonuniformity are investigated in this paper. The results show that the switching characteristics are degraded by the CR nonuniformity, especially in the case of large InAs/GaSb band offset. This paper a... View full abstract»

• 1-kb FinFET Dielectric Resistive Random Access Memory Array in $1times$ nm CMOS Logic Technology for Embedded Nonvolatile Memory Applications

Publication Year: 2016, Page(s):4273 - 4278
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A new two-transistor logic resistive random-access memory (RRAM) cell with a 16-nm standard FinFET CMOS logic platform that is fully compatible with the CMOS process is proposed and demonstrated in a 1-kb FinFET dielectric RRAM (FIND RRAM) array. The new 16-nm FIND RRAM comprises two logic standard FinFET transistors with a HfO2-based composite resistive gate dielectric film as the storage node in... View full abstract»

• Postcycling Degradation in Metal-Oxide Bipolar Resistive Switching Memory

Publication Year: 2016, Page(s):4279 - 4287
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Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cyclinginduced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as t... View full abstract»

• Modifying Indium-Tin-Oxide by Gas Cosputtering for Use as an Insulator in Resistive Random Access Memory

Publication Year: 2016, Page(s):4288 - 4294
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In this paper, indium-tin-oxide (ITO) was used to act as both insulator and top electrode in resistive random access memory (RRAM) on identical bottom substrates. This is achieved by cosputtering an ITO target with nitride (N2) or oxygen (O2) gas as the insulator; then capping by an ITO electrode, such that both the rectifier and RRAM characteristics can be achieved before an... View full abstract»

• Self-Selection RRAM Cell With Sub- $\mu \text{A}$ Switching Current and Robust Reliability Fabricated by High- $K$ /Metal Gate CMOS Compatible Technology

Publication Year: 2016, Page(s):4295 - 4301
Cited by:  Papers (2)
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A high-K/metal gate (HKMG)-stack (TiN/Al-dopedHfOx/SiO2/Si)-based bipolar resistive random access memory (RRAM) cell is proposed and fabricated by 28/20-nm HKMG CMOS compatible technology. Robust reliability behaviors (retention at 200°C 4 × 104 s and endurance 105 cycles) and ultralow switching current (<;0.1 μA for RESET and <... View full abstract»

• Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage

Publication Year: 2016, Page(s):4302 - 4308
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Four write stability metrics for the characterization of six-transistor SRAM cells were experimentally evaluated and compared at low supply voltage (VDD). A silicon-on-thin-BOX technology with reduced body doping was used to achieve low voltage operation. It was confirmed that both bitline and wordline methods are preferable in that they yield metrics that follow normal distributions, w... View full abstract»

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy