# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 26

Publication Year: 2016, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2016, Page(s): C2
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• ### An Efficient Switched-Capacitor DC-DC Buck Converter for Self-Powered Wearable Electronics

Publication Year: 2016, Page(s):1557 - 1566
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This paper introduces an efficient reconfigurable, multiple voltage gain switched-capacitor dc-dc buck converter as part of a power management unit for wearable electronics. The proposed switched-capacitor converter has an input voltage of 0.6 V to 1.2 V generated from an energy harvesting source. The switched-capacitor converter utilizes pulse frequency modulation to generate multiple regulated o... View full abstract»

• ### A Pseudo Single-Stage Amplifier With an Adaptively Varied Medium Impedance Node for Ultra-High Slew Rate and Wide-Range Capacitive-Load Drivability

Publication Year: 2016, Page(s):1567 - 1578
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This paper presents a pseudo single-stage (PSS) amplifier with an adaptively varied medium impedance node to achieve an ultra-high slew rate (SR) and at the same time stable operation in a wide capacitive load range. Owing to the characteristics of the proposed technique, this amplifier achieves a 1.1-to-8.67 V/μs slew rate and a 0.01-to-1.66 MHz unity gain frequency over a 0.1-to-15 nF cap... View full abstract»

• ### An Ultra-Wideband Digitally Programmable Power Amplifier With Efficiency Enhancement for Cellular and Emerging Wireless Communication Standards

Publication Year: 2016, Page(s):1579 - 1591
Cited by:  Papers (1)
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The design and measurements of a fabricated novel digitally programmable wideband power amplifier (PA) are presented. The PA is made suitable for use in all communication standards, including GSM, 3G, LTE and Femto-cells, offering a bandwidth of several octaves covering presently 300 MHz to 3.5 GHz. It meets power, efficiency and linearity specifications. The amplifier showed excellent performance... View full abstract»

• ### A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector

Publication Year: 2016, Page(s):1592 - 1604
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A 400 Mb/s ~2.5 Gb/s referenceless clock and data recovery (CDR) IC is presented. This paper shows that the half-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability in itself. By using this intrinsic frequency detection capability of the half-rate linear PD, a CDR can be implemented in the single loop architecture without bot... View full abstract»

• ### Time-of-Arrival Measurement Using Adaptive CMOS IR-UWB Range Finder With Scalable Resolution

Publication Year: 2016, Page(s):1605 - 1615
Cited by:  Papers (1)
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This paper introduces an adaptive CMOS impulse-radio ultra-wideband (IR-UWB) range finder with scalable resolution for localization applications and presents a brief demonstration of its operation. The distance resolution of the proposed range finder can be adapted to the ranging environment using a two-step time-to-digital converter (TDC) with scalable delay cells. Using the scalable time resolut... View full abstract»

• ### A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching

Publication Year: 2016, Page(s):1616 - 1627
Cited by:  Papers (1)
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A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy), total capacitance and static performance (INL & DNL) of the proposed scheme are reduced by 98.08%, 7... View full abstract»

• ### An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS

Publication Year: 2016, Page(s):1628 - 1638
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This paper demonstrates an asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) architecture with an embedded passive gain technique for lowpower and high-speed operation. The proposed passive gain technique relaxes the noise requirement of the comparator and reuses the existing capacitor DAC in SAR for minimal overhead. An additional time-out scheme is adopted to... View full abstract»

• ### A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter

Publication Year: 2016, Page(s):1639 - 1651
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This work proposes a nonuniform sampling analog-to-digital converter (ADC) architecture that incorporates a reconfigurable digital anti-aliasing (AA) filter in the asynchronous digital domain. Considering applications where the signal frequency, bandwidth, or activity may significantly vary over time and operating conditions, it provides high flexibility, relaxes analog AA filter requirements, ada... View full abstract»

• ### Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read

Publication Year: 2016, Page(s):1652 - 1660
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This paper proposes a novel boosted voltage sensing (BVS) scheme that substantially improves the resiliency of STT-MRAMs against variations in read accesses based on bitline voltage sensing, and on a wide range of voltages. The BVS scheme mitigates the impact of variations in the senseamp and the reference voltage generation, and is based on switched-capacitor voltage boosters. The related area-pe... View full abstract»

• ### Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing

Publication Year: 2016, Page(s):1661 - 1672
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OpenFlow, the main protocol for software-defined networking (SDN) advocated by Google, requires multiple flow tables with long and variable rule lengths. For fast packet forwarding, using ternary content-addressable memory (TCAM) as implementation of lookup-table has displayed superior performance in executing the conventional packet classification algorithms. However, applying traditional TCAM de... View full abstract»

• ### New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements

Publication Year: 2016, Page(s):1673 - 1681
Cited by:  Papers (1)
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This paper presents novel designs of static dual-edge-triggered (DET) flip-flops that exhibit unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are presented including two high-performance designs and designs that improve upon common Latch-MUX DET flip-flops so that none of their internal circuit nodes follow changes in the input signal. A common characteristic of t... View full abstract»

• ### A Simple and Reliable System to Detect and Correct Setup/Hold Time Violations in Digital Circuits

Publication Year: 2016, Page(s):1682 - 1689
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In this article, a fully digital system to detect and correct setup/hold time violations in digital circuits, is presented. The proposed system benefits from simple, low-power, small-area, and easy-to-modify design. The system is composed of two separate blocks, detector and corrector connected through a 2-bit control signal. The detector is placed near flip-flops or memory elements and sends cont... View full abstract»

• ### A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression

Publication Year: 2016, Page(s):1690 - 1700
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This paper proposes a power and area efficient Laplacian Pyramid processing engine (LPPE) for real-time portable image/video processing applications. On the architecture level, an adaptive data compression technique is proposed to reduce the power and area of FIFOs in the LPPE while maintaining small mean square error (MSE). A new filtering extension method is proposed to reduce the output errors ... View full abstract»

• ### Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters

Publication Year: 2016, Page(s):1701 - 1713
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Most of the research on the implementation of finite impulse response (FIR) filter so far focuses on the optimization of the multiple constant multiplication (MCM) block. But it is observed that the product-accumulation section often contributes the major part of the critical path, such that the timing optimization of MCM block does not impact significantly on the overall speedup of the FIR filter... View full abstract»

• ### Distributed Federated Kalman Filter Fusion Over Multi-Sensor Unreliable Networked Systems

Publication Year: 2016, Page(s):1714 - 1725
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This paper is concerned with the problem of distributed federated Kalman filter fusion (DFKFF) for a class of multi- sensor unreliable networked systems (MUNSs) with uncorrelated noises. An optimal DFKFF algorithm of MUNSs without buffer is presented, and rigorously proved to be equivalent to centralized optimal Kalman filter fusion (COKFF) algorithm of MUNSs without buffer. Finite length buffers ... View full abstract»

• ### High-Accuracy Compressed Sensing Decoder Based on Adaptive $(\ell_{0},\ell_{1})$ Complex Approximate Message Passing: Cross-layer Design

Publication Year: 2016, Page(s):1726 - 1736
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Compressed sensing (CS) allows a signal that is sparse in certain domain to be acquired and reconstructed accurately with only a small number of samples. In this paper, we propose an adaptive (ℓ0, ℓ1) complex approximate message passing (CAMP) algorithm and its hardware implementation for complex-valued sparse signal recovery. Compared with the existing CAMP alg... View full abstract»

• ### A New Representation of FFT Algorithms Using Triangular Matrices

Publication Year: 2016, Page(s):1737 - 1745
Cited by:  Papers (1)
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In this paper we propose a new representation for FFT algorithms called the triangular matrix representation. This representation is more general than the binary tree representation and, therefore, it introduces new FFT algorithms that were not discovered before. Furthermore, the new representation has the advantage that it is simple and easy to understand, as each FFT algorithm only consists of a... View full abstract»

• ### A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS

Publication Year: 2016, Page(s):1746 - 1757
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This paper discusses a systematic study of electrostatic discharge (ESD) protection circuit co-design and analysis technique for high-frequency and high-speed ICs in 28 nm CMOS. The comprehensive ESD-IC co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, backend interconnect characterization, parasitic ESD parameter extraction, ESD failure analysis and ES... View full abstract»

• ### System Design for Direct RF-to-Digital $DeltaSigma$ Receiver

Publication Year: 2016, Page(s):1758 - 1770
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The Direct RF-to-Digital ΔΣ receiver has emerged as an attractive solution for multi-band multi-standard wireless applications. This architecture is a direct RF to baseband digitizer with RF feedback from baseband to RF stages. The presence of the RF blocks such as the low noise amplifier and down-conversion mixer inside the loop filter significantly relaxes their linearity requireme... View full abstract»

• ### Structural Controllability of Temporally Switching Networks

Publication Year: 2016, Page(s):1771 - 1781
Cited by:  Papers (4)
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In this paper, the controllability problem is addressed for temporally switching networks and the associated temporally switching systems. The state controllability criterion of temporally switching systems is firstly obtained, which stands for structural controllability of temporally switching networks with the same structure. With a new temporal interpretation of the dilation and intersection co... View full abstract»

• ### IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors

Publication Year: 2016, Page(s): 1782
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• ### Call for Papers

Publication Year: 2016, Page(s): 1783
| PDF (34 KB)
• ### Open Access

Publication Year: 2016, Page(s): 1784
| PDF (410 KB)

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK