# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 23 of 23

Publication Year: 2016, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Publication Year: 2016, Page(s): C2
| PDF (40 KB)
• ### A Novel 10-Bit 2.8-mW TDC Design Using SAR With Continuous Disassembly Algorithm

Publication Year: 2016, Page(s):909 - 913
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This brief introduces a successive approximation time-to-digital converter based on a novel algorithm denoted as successive approximation register with continuous disassembly (SAR-CD). The main advantage of the proposed SAR-CD algorithm is that it moves the conditioning between the evaluated bits to the digital domain, after all the bits are evaluated. Simulation results show promising enhancement... View full abstract»

• ### Noise Figure Optimization Tool for Millimeter-Wave Receivers at Near- $f_{max}$ Frequencies

Publication Year: 2016, Page(s):914 - 918
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This brief presents an evaluation tool of the noise figure reduction that can be achieved by adding a low-noise amplifier in a near- fmax frequency receiver. After choosing a suitable topology and assessing its frequency dependence, an analytical derivation is carried out and preliminary frequency constraints are found. The analytical assessment is followed by a practical example using ... View full abstract»

• ### Compensation Method for Multistage Opamps With High Capacitive Load Using Negative Capacitance

Publication Year: 2016, Page(s):919 - 923
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It is shown that negative capacitance (NC) circuits can be systematically used to improve the gain-bandwidth product of the operational amplifiers (opamps). The NC circuit moves the nondominant pole of the opamp to higher frequency by decreasing the parasitic capacitance of the critical node. The impedance at the input of the NC circuits is neither purely capacitive nor negative at all frequencies... View full abstract»

• ### A 10-b 200-kS/s 250-nA Self-Clocked Coarse–Fine SAR ADC

Publication Year: 2016, Page(s):924 - 928
Cited by:  Papers (1)
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A 10-b ultralow-power successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a standard 0.18- μm CMOS technology is described. The architecture consists of a coarse and a fine SAR ADC. The 2-b coarse SAR presets the two MSB capacitive arrays of the fine SAR, thus avoiding the largest sources of dynamic power consumption. The use of two low-resolution compar... View full abstract»

• ### Impedance-Sensing CMOS Chip for Noninvasive Light Detection in Integrated Photonics

Publication Year: 2016, Page(s):929 - 933
Cited by:  Papers (3)
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A 100-MHz-bandwidth multichannel instrument-on-chip for noninvasive light monitoring in photonic circuits by means of the impedance sensing of the waveguide (WG) conductance variation is presented. The low-noise front-end allows accessing the WG conductance with very high sensitivity and tracking its variation upon changes of the photon flux with a resolution better than 10 pS, i.e., down to -30 d... View full abstract»

• ### An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search

Publication Year: 2016, Page(s):934 - 938
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This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS... View full abstract»

• ### Very Sensitive Low-Noise Active-Reset CMOS Image Sensor With In-Pixel ADC

Publication Year: 2016, Page(s):939 - 943
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Low light imaging is being researched intensively. The applications of increased sensitivity sensors expand to biomedicine, security, and communications providing low-cost and effective alternatives to common imaging techniques based on microscopes, intensifiers, etc. Lowering the inherent noise floor and achieving a higher sensitivity in a complementary metal-oxide semiconductor (CMOS) sensor are... View full abstract»

• ### A Simple Nonlinear Circuit Contains an Infinite Number of Functions

Publication Year: 2016, Page(s):944 - 948
Cited by:  Papers (4)
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The complex dynamics of a simple nonlinear circuit contains an infinite number of functions. Specifically, this brief shows that the number of different functions that a nonlinear or chaotic circuit can implement exponentially increases as the circuit evolves in time, and this exponential increase is quantified with an exponent that is named the computing exponent. This brief argues that a simple ... View full abstract»

• ### Low-Complexity MIMO Detection: A Mixture of Basic Techniques for Near-Optimal Error Rate

Publication Year: 2016, Page(s):949 - 953
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The research of finding better ways for multiple-input multiple-output signal detection is important and still goes on. In this brief, a low-complexity detection method mainly with basic and hardware-friendly operations, i.e., reduced-complexity zero forcing, successive interference cancelation, and single-symbol maximum likelihood detection with M- algorithm, is proposed. Essentially, this detect... View full abstract»

• ### Implementation of a Near-Optimal Detector for Spatial Modulation MIMO Systems

Publication Year: 2016, Page(s):954 - 958
Cited by:  Papers (1)
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This brief presents a hardware implementation of a detector for spatial modulation multiple-input multiple-output (SM-MIMO) communication systems. The proposed detector employs the signal-vector-based list detection method, but the original method is modified to realize a low-complexity implementation. In addition, the proposed detector is designed based on the dual-data-path architecture, in whic... View full abstract»

• ### Resource Allocation for Heterogeneous Traffic in Complex Communication Networks

Publication Year: 2016, Page(s):959 - 963
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This brief introduces an optimal resource allocation scheme for heterogeneous traffic in communication networks with the viewpoint of complex system networks. Since both the transmission flow rate and processing capability distribution can affect the traffic performance, we formulate an optimization problem with the main goal of maximizing the network utility, subject to constraints on the node co... View full abstract»

• ### Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution

Publication Year: 2016, Page(s):964 - 968
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This brief describes a charge redistribution transient cell supply voltage collapse write assist (CR-TVC-WA) for static random access memory. Although wordline underdrive read assist is a requisite for stable read operations in deep submicrometer technologies, it significantly degrades the write ability. To overcome this problem, a transient cell supply voltage (VDD,CELL) collapse write... View full abstract»

• ### Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations

Publication Year: 2016, Page(s):969 - 973
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In modern embedded processor systems, energy efficiency is a critical issue. Unfortunately, to avoid cache memory (SRAM) faults from dynamic variations, caches generally operate at an elevated voltage to build a safety guardband that decreases energy efficiency. To address this issue, tolerating SRAM faults to eliminate the safety of a guardband without frequency scaling may be a viable solution. ... View full abstract»

• ### The Serial Commutator FFT

Publication Year: 2016, Page(s):974 - 978
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This brief presents a new type of fast Fourier transform (FFT) hardware architectures called serial commutator (SC) FFT. The SC FFT is characterized by the use of circuits for bit-dimension permutation of serial data. The proposed architectures are based on the observation that, in the radix-2 FFT algorithm, only half of the samples at each stage must be rotated. This fact, together with a proper ... View full abstract»

• ### Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

Publication Year: 2016, Page(s):979 - 983
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Two-dimensional (2-D) convolution is a widely used operation in image processing and computer vision, characterized by intensive computation and frequent memory accesses. Previous efforts to improve the performance of field-programmable gate array (FPGA) convolvers focused on the design of buffering schemes and on minimizing the use of multipliers. A recently proposed recurrently decomposable (RD)... View full abstract»

• ### An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor

Publication Year: 2016, Page(s):984 - 988
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Aiming at electrocardiogram (ECG) monitoring systems for wearable and implantable health-care applications, an ultralow-power and low-cost wavelet-based ECG processor is presented in this brief. This processor can work at subthreshold voltage and further save energy by using voltage overscaling (VOS) and algorithmic noise tolerance (ANT). As to the ANT mechanism, we propose a weighted-average-bila... View full abstract»

• ### Affine Projection Subband Adaptive Filter With Low Computational Complexity

Publication Year: 2016, Page(s):989 - 993
Cited by:  Papers (2)
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The affine projection algorithm (APA) and the normalized subband adaptive filter (NSAF) have been proposed to improve the convergence rate of the normalized least mean square algorithm for colored input signals. Recently, the improved multiband-structured subband adaptive filter (IMSAF) has been advanced, combining the APA and NSAF optimization approaches. The use of the IMSAF may result in accele... View full abstract»

• ### UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications

Publication Year: 2016, Page(s):994 - 998
Cited by:  Papers (1)
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A challenging verification and optimization problem in computer arithmetic and embedded systems is error analysis (EA) of fixed-point polynomial data-flow graphs (DFGs). This brief presents an EA framework to compute the error measure maximum mismatch of feedforward fixed-point polynomial DFGs. Our idea to reduce the overestimation keeping efficiency is introducing a unified analytical framework f... View full abstract»

• ### An Improved Signed Digit Representation Approach for Constant Vector Multiplication

Publication Year: 2016, Page(s):999 - 1003
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In this brief, the multiplier-free implementation of the constant vector multiplication is reexamined. A novel improved signed digit representation technique is proposed to overcome the two main drawbacks of the current multiplier-free techniques: 1) computational redundancy and 2) circuit irregularity. The fundamental difference between the proposed technique and the existing multiplier-free tech... View full abstract»

• ### Ultralow-Area Hysteretic Control LDO With Sub-1- $mutext{A}$ Quiescent Current

Publication Year: 2016, Page(s):1004 - 1008
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An ultrasmall voltage regulator utilizing bang-bang on-off control is proposed as a low-quiescent-current regulator. The circuit was fabricated using 0.13-μm CMOS technology and occupies 35 μm × 35 μm. It consumes less than 1 μA in the idle state and supplies up to 100 μA at 1.8 V from an unregulated supply that varies from 1.9 to 3.3 V, making it suitable... View full abstract»

• ### IEEE Circuits and Systems Society Information

Publication Year: 2016, Page(s): C3
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## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org