# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 54

Publication Year: 2016, Page(s):C1 - 3818
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2016, Page(s): C2
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• ### A Mini Review of Neuromorphic Architectures and Implementations

Publication Year: 2016, Page(s):3819 - 3829
Cited by:  Papers (5)
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Neuromorphic architectures are hardware systems that aim to use the principles of neural function for their basis of operation. Their goal is to harness biologically inspired concepts such as weighted connections, activation thresholds, short-and long-term potentiation, and inhibition to solve problems in distributed computation. Compared with today's methods of emulating neural function in softwa... View full abstract»

• ### A Comparative Study of Defect Energy Distribution and Its Impact on Degradation Kinetics in GeO2/Ge and SiON/Si pMOSFETs

Publication Year: 2016, Page(s):3830 - 3836
Cited by:  Papers (1)
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The high mobility germanium (Ge) channel is considered as a strong candidate for replacing Si in pMOSFETs in the near future. It has been reported that the conventional power-law degradation kinetics of Si devices is inapplicable to Ge. In this paper, further investigation is carried out on defect energy distribution, which clearly shows that this is because the defects in GeO2/Ge and S... View full abstract»

• ### Suspended Diamond-Shaped Nanowire With Four {111} Facets for High-Performance Ge Gate-All-Around FETs

Publication Year: 2016, Page(s):3837 - 3843
Cited by:  Papers (2)
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A feasible pathway to scale germanium (Ge) FETs in future technology nodes has been proposed using the tunable diamond-shaped Ge nanowire (NW). The Ge NW was obtained through a simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The different etching selectivity of surface orientations for Cl2 and HBr was employed for the three-step isotro... View full abstract»

• ### Conductance-to-Current-Ratio-Based Parameter Extraction in MOS Leakage Current Models

Publication Year: 2016, Page(s):3844 - 3850
Cited by:  Papers (1)
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A new procedure to extract the parameters of mathematical models that describe charge flow phenomena through thin dielectrics is proposed for characterizing undesirable leakage current mechanisms in modern MOSFETs' gates. The procedure's basis is the small signal conductance-to-current ratio of the I-V characteristics. It is an alternative to, and has advantages over, the other presently used meth... View full abstract»

• ### Rapid and Accurate $C$ – $V$ Measurements

Publication Year: 2016, Page(s):3851 - 3856
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We report a new technique for the rapid measurement of full capacitance-voltage (C-V) characteristic curves. The displacement current from a 100-MHz applied sine wave, which swings from accumulation to strong inversion, is digitized directly using an oscilloscope from the MOS capacitor under test. A C-V curve can be constructed directly from this data but is severely distorted due to nonideal beha... View full abstract»

• ### 3-D Analytical Model for Short-Channel Triple-Gate Junctionless MOSFETs

Publication Year: 2016, Page(s):3857 - 3863
Cited by:  Papers (2)
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An analytical model for short-channel triple-gate junctionless MOSFETs in the full operation regimes has been presented based on the solution of 3-D Poisson's equation. A separation approach is developed to solve 3-D Poisson's equation, and the contribution of the fixed and mobile charges can be considered separately. Besides, a fitting parameter βf is introduced to characterize the couplin... View full abstract»

• ### Analytical Model of the Parasitic Bipolar Junction Transistor in Low-Doped Double-Gate FinFETs for Pass-Gate Circuits

Publication Year: 2016, Page(s):3864 - 3868
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The transient parasitic bipolar effect in floating-body double-gate FinFETs with low-doped bodies is analytically modeled. The obtained analytical transient bipolar current and charge models have predictive power for various device structures. These models are applicable when the majority carrier concentration in accumulation conditions noticeably exceeds the body doping concentration. The physica... View full abstract»

• ### High-Performance Asymmetric Underlap Ge-pTFET With Pocket Implantation

Publication Year: 2016, Page(s):3869 - 3875
Cited by:  Papers (2)
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This paper reports a systematic methodology to enhance the performance of germanium p-type tunnel FETs (Ge-pTFETs) using a p+ pocket implant at the source end of the channel and an underlap region at the drain end. The numerical device simulation results show that an optimized drain-underlap region reduces the off-state leakage current (IOFF) of 50-nm Ge-pTFETs to about 3.27 ... View full abstract»

• ### Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs by Strain Engineering Design

Publication Year: 2016, Page(s):3876 - 3881
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The piezoelectric polarization of the AlGaN/GaN high-electron-mobility transistors (HEMTs) is strongly related to the strain state in the active area. Therefore, understanding the strain behavior inside the channel is crucial to the device electrical performance improvement of devices. This paper, for the first time, reveals the potential of optimizing flip-chip structures with active-region bumps... View full abstract»

• ### W-Band MMIC PA With Ultrahigh Power Density in 100-nm AlGaN/GaN Technology

Publication Year: 2016, Page(s):3882 - 3886
Cited by:  Papers (3)
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A three-stage W-band GaN monolithic microwave integrated circuit power amplifier (MMIC PA) is reported. Electron-beam lithography has been employed to define a 100-nm T-shaped gate on the AlGaN/GaN HEMT structure with ultrahigh aluminum content. The MMIC PA offers a peak small signal gain of 16.7 dB in the 90-97 GHz bandwidth. Moreover, it achieves a peak 1.66-W (32.2 dBm) output power at 93 GHz i... View full abstract»

• ### Influence on Noise Performance of GaN HEMTs With In Situ and Low-Pressure-Chemical-Vapor-Deposition SiNx Passivation

Publication Year: 2016, Page(s):3887 - 3892
Cited by:  Papers (1)
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High-frequency and low-frequency noise (LFN) performance of GaN high electron-mobility transistors (HEMTs), passivated with SiNx deposited by either in situ or low-pressure-chemical-vapor-deposition (LPCVD), are compared. From 8-26 GHz, the LPCVD sample has a lower minimum noise figure (1 dB at 8 GHz) because of lower power spectral density of noise sources and less transconductance (gm) dispersio... View full abstract»

• ### Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology

Publication Year: 2016, Page(s):3893 - 3899
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The device and circuit performance of a 20-nm gate length InGaAs and Ge hybrid CMOS based on an implant free quantum well (QW) device architecture is studied using a multiscale approach combining ensemble Monte Carlo simulation, drift-diffusion simulation, compact modeling, and TCAD mixed-mode circuit simulation. We have found that the QW and doped substrate, used in the hybrid CMOS, help to reduc... View full abstract»

• ### Monte Carlo Study of 2-D Capacitance Fringing Effects in GaAs Planar Schottky Diodes

Publication Year: 2016, Page(s):3900 - 3907
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Nanometer scale planar Schottky barrier diodes (SBDs) with realistic geometries have been studied by means of a 2-D ensemble Monte Carlo simulator. The topology of the devices studied in this paper is based in real planar GaAs SBDs used in terahertz applications, such as passive frequency mixing and multiplication, in which accurate models for the diode capacitance are required. The intrinsic capa... View full abstract»

• ### Study of Gate Width Influence on Extrinsic Transconductance in AlGaN/GaN Heterostructure Field-Effect Transistors With Polarization Coulomb Field Scattering

Publication Year: 2016, Page(s):3908 - 3913
Cited by:  Papers (2)
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AlGaN/GaN heterostructure FETs with the same gate length and different gate widths were fabricated, and the extrinsic transconductance was measured. The device with a wider gate width shows a lower peak value, but a slower drop of extrinsic transconductance. This phenomenon is attributed to the influence of polarization Coulomb field (PCF) scattering, which originates from the irregular distributi... View full abstract»

• ### Switching Time and Stability Evaluation for Writing Operation of STT-MRAM Crossbar Array

Publication Year: 2016, Page(s):3914 - 3921
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The dynamic characteristics of a spin transfer torque magnetoresistive random access memory crossbar array during write operations were investigated. A spin transfer torque magnetic tunnel junction was combined with a two-terminal selector device instead of a three-terminal CMOS transistor in the crossbar array architecture. The characteristics of the crossbar array architecture were investigated ... View full abstract»

• ### A Phase Change Memory Cell With Metal Nitride Liner as a Resistance Stabilizer to Reduce Read Current Noise for MLC Optimization

Publication Year: 2016, Page(s):3922 - 3927
Cited by:  Papers (2)
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Relatively large noise of phase change material is one of the obstacles for realization of multilevel cell (MLC) using phase change memory (PCM) technology. We experimentally verify that the noise in PCM can be lowered as much as ~4 times by a novel PCM cell which utilizes metal nitride liner to provide an alternative conductive path to the amorphous region with large noise. Program-and-verify (PN... View full abstract»

• ### Performance and Reliability of TiO2/ZrO2/TiO2 (TZT) and AlO-Doped TZT MIM Capacitors

Publication Year: 2016, Page(s):3928 - 3935
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Metal-insulator-metal capacitors for dynamic random access memory applications have been realized using TiO2/ZrO2/TiO2 (TZT) and AlO-doped TZT [TiO2/ZrO2/AlO/ ZrO2/TiO2 (TZAZT) and TiO2/ZrO2/AlO/ZrO2/AlO/ZrO2/TiO2 (TZAZAZT)] dielectric stacks. High-capacitance densiti... View full abstract»

• ### Nanocrystalline ZnO TFTs Using 15-nm Thick Al2O3 Gate Insulator: Experiment and Simulation

Publication Year: 2016, Page(s):3936 - 3943
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Thin-film transistors were fabricated using 45-nm thick ZnO deposited by pulsed laser deposition and 15-nm thick Al2O3 gate insulator deposited by atomic layer deposition. A 1-D model with a constant density of interface states above and below the conduction band edge is used to explain the current-voltage characteristic. This model does not create distortion of transconducta... View full abstract»

• ### High-Voltage Amorphous InGaZnO TFT With Al2O3 High- $k$ Dielectric for Low-Temperature Monolithic 3-D Integration

Publication Year: 2016, Page(s):3944 - 3949
Cited by:  Papers (3)
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On-chip high-voltage (HV) power management integrated circuits would deliver smaller form factor, lower system cost, higher power efficiency, and suppressed noise in system-on-chip designs. A reliable HV amorphous-indium- gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology has been presented for potential applications of monolithic 3-D integration on CMOS. By using a process temperat... View full abstract»

• ### Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation

Publication Year: 2016, Page(s):3950 - 3957
Cited by:  Papers (7)
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A novel device configuration is presented for doping-less charge plasma tunnel FET (TFET) for suppression of ambipolar nature with improved high-frequency figures of merit. For this, the drain electrode, which is used to induce n+ drain region, is separated into two sections of high and low work functions. The work function of the drain electrode section near to channel is considered re... View full abstract»

• ### Indium-Zinc-Oxide Neuron Thin Film Transistors Laterally Coupled by Sodium Alginate Electrolytes

Publication Year: 2016, Page(s):3958 - 3963
Cited by:  Papers (1)
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Neuromorphic devices are of great significance for capturing the computation power of the neural network with ultralow energy consumption and extremely high efficiency. Here, multigate indium-zinc-oxide-based neuron thin film transistors laterally coupled by sodium alginate electrolyte films were fabricated polyethylene terephthalate substrates for neuromorphic system application. The dynamic rang... View full abstract»

• ### Dynamic-Gate-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Publication Year: 2016, Page(s):3964 - 3970
Cited by:  Papers (1)
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In this paper, degradation behaviors of bridged-grain (BG) polycrystalline silicon (poly-Si) thin-hlm transistors (TFTs) are systematically characterized and investigated. Device degradation exhibits a two-stage behavior, which is related to pulse falling time (tf). A faster tf brings a larger ON-current (ION) increase in the first stage and a larger ION... View full abstract»

• ### Thin-Film Single-Crystal Schottky Diodes for IR Detection and Beyond

Publication Year: 2016, Page(s):3971 - 3976
Cited by:  Papers (3)
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Thin-film p-type Co-Si and n-type Cr-Si Schottky diodes have been fabricated, in which a thin silicon layer is sandwiched between the anode and the cathode of the diodes, in a vertical configuration. The thicknesses of the silicon are 70 and 40 nm, for Co-Si and Cr-Si diodes, respectively. The thin layer significantly reduces the series resistance and the vertical structure reduces the parasitic c... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

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## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy