By Topic

IEEE Transactions on Computers

Issue 9 • Sep 1994

Filter Results

Displaying Results 1 - 13 of 13
  • Reliable butterfly distributed-memory multiprocessors

    Publication Year: 1994, Page(s):1004 - 1013
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB)

    Since the butterfly network possesses various attractive topological properties and its constituent node has a fixed degree, independent of the system size, interconnecting processors in accordance with the butterfly topology to construct a distributed-memory multiprocessor is advantageous, especially for a large sized system. Every butterfly node in a multiprocessor so constructed is a processor,... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Distributed reset

    Publication Year: 1994, Page(s):1026 - 1038
    Cited by:  Papers (103)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1068 KB)

    A reset subsystem is designed that can be embedded in an arbitrary distributed system in order to allow the system processes to reset the system when necessary. Our design is layered, and comprises three main components: a leader election, a spanning tree construction, and a diffusing computation. Each of these components is self-stabilizing in the following sense: if the coordination between the ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The susceptibility of programs to context switching

    Publication Year: 1994, Page(s):994 - 1003
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    Modern memory systems are composed of several levels of caching. The design of these levels is largely an empirical practice. One highly-effective empirical method is the single-pass method wherein all caches in a broad design space are evaluated in one pass over the trace. Multiprogramming degrades memory system performance since context switching reduces the effectiveness of cache memories. Few ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Probabilistic clock synchronization in large distributed systems

    Publication Year: 1994, Page(s):1106 - 1112
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    Clock synchronization within a distributed system is a problem that has been studied extensively in recent years. Of the many solutions proposed thus far, probabilistic synchronization algorithms provide arguably the best compromise between tightness of synchronization and overhead imposed on the system. The main drawbacks of probabilistic algorithms are the requirement of a master/slave organizat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Deleting vertices to bound path length

    Publication Year: 1994, Page(s):1091 - 1096
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Examines the vertex deletion problem for weighted directed acyclic graphs (WDAGs). The objective is to delete the fewest number of vertices so that the resulting WDAG has no path of length >δ. Several simplified versions of this problem are shown to be NP-hard. However, the problem is solved in linear time when the WDAG is a rooted tree, and in quadratic time when the WDAG is a series-par... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An optimal retry policy based on fault classification

    Publication Year: 1994, Page(s):1014 - 1025
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1024 KB)

    An optimal retry policy in a computer system is usually derived under the unrealistic assumption that fault characteristics are known a priori and remain unchanged throughout the mission lifetime. In such a case, the optimal retry period depends only upon the system's status at the time of fault detection. We propose to remedy this deficiency by formulating the optimal retry problem as a Bayesian ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Load sharing with consideration of future task arrivals in heterogeneous distributed real-time systems

    Publication Year: 1994, Page(s):1076 - 1090
    Cited by:  Papers (18)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1344 KB)

    In a heterogeneous distributed real-time system, transferring an unguaranteed task at a node to another node currently with the most abundant resources is not necessarily the best decision. We propose a new load sharing (LS) algorithm for real-time applications which takes into account the effect of future task arrivals on locating the best receiver for each unguaranteed task. Upon arrival of a ta... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comparison of reconfiguration schemes for the C2SC MIN operating in the broadcast mode

    Publication Year: 1994, Page(s):1112 - 1119
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    The complementary two-stage cube (C2SC) provides four paths between every source and destination pair so that all single faults and many multiple faults can be tolerated. One of the key issues in multiple-path multistage interconnection networks (MIN's) is the manner in which rerouting is achieved when the network has faults. In this paper, we present four reconfiguration schemes for broadcast con... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiple fault detection in parity checkers

    Publication Year: 1994, Page(s):1096 - 1099
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Parity checkers are widely used in digital systems to detect errors when systems are in operation. Since parity checkers are monitoring circuits, their reliability must be guaranteed by performing a thorough testing. In this work, multiple fault detection of parity checkers is investigated. We have found that all multiple stuck-at faults occurring on a parity tree can be completely detected using ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reliability models for fault-tolerant private network applications

    Publication Year: 1994, Page(s):1039 - 1053
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1224 KB)

    A private or corporate network connects the offices of a single large organization, such as an airline or a bank, using leased private lines. To improve the reliability of network applications, fault-tolerance can be incorporated directly into the private network. In this paper, we use a state-space model to capture the effect of dynamic rerouting and repair and investigate the effect on reliabili... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the role of hardware reset in synchronous sequential circuit test generation

    Publication Year: 1994, Page(s):1100 - 1105
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    The existence of hardware reset facilitates the test generation process for synchronous sequential circuits, as compared to test generation that starts from an unspecified initial state. Conventionally, therefore, when hardware reset is available, it is used to reset all state variables to predetermined values, conventionally 0, before a test sequence is applied. In this paper, we show that full h... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Diagnosability of enhanced hypercubes

    Publication Year: 1994, Page(s):1054 - 1061
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    An enhanced hypercube is obtained by adding 2n-1 more links to a regular hypercube of 2n processors. It has been shown that enhanced hypercubes have very good improvements over regular hypercubes in many measurements such as mean internode distance, diameter and traffic density. This paper proves that in the aspect of diagnosability, enhanced hypercubes also achieve improveme... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A highly OR-parallel inference machine (Multi-ASCA) and its performance evaluation: an architecture and its load balancing algorithms

    Publication Year: 1994, Page(s):1062 - 1075
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1188 KB)

    An architecture and its four load balancing algorithms for a highly OR-parallel inference machine are proposed, and its performance is evaluated in a trace-driven simulation study. This inference machine consists of a large number of processing elements (PEs) with serial I/O links directly connected to each other in a simply modified mesh network. Each PE is a high-speed sequential Prolog processo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org