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Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on

Issue 3 • Date Sep 1994

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Displaying Results 1 - 24 of 24
  • Chip manufacturing: matching production plan with customer requirements

    Publication Year: 1994 , Page(s): 446 - 451
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    Manufacturing chips is a long process that starts by deciding how many chips of each type a wafer to be launched in production must contain in order to meet customer requirements. The total number of chips per wafer is constant, and any mix of chip types is allowed on a wafer. Two levels of failure may arise during the manufacturing process, namely 1) the ones that result in rejecting a wafer and, as a consequence, all the chips contained in this wafer, and 2) the failures that result in rejecting chips individually. We know the probability of a wafer to fail, as well as the probability of a chip of any type to be rejected. The goal is to minimize the number of wafers to launch in production in order to meet the customer requirements with a given probability. In this paper, we propose an efficient heuristic algorithm that leads to a near-optimal solution. Several numerical examples illustrate this algorithm View full abstract»

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  • Squeegee deformation study in the stencil printing of solder pastes

    Publication Year: 1994 , Page(s): 470 - 476
    Cited by:  Papers (7)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    We report on the results of an experimental comparison of different types of squeegee blade used in the stencil printing of solder pastes for reflow soldering in SMT, concentrating on paste heights (scooping) and printing defects. We show how our experimental results for squeegee deformation into stencil apertures lead to the construction of a model for squeegee deformation. The model takes into account the force on the squeegee due to solder paste flow and some of the non-Newtonian properties of the solder paste. An explanation is proposed for the differences in paste heights between apertures of different orientations View full abstract»

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  • A 5 V-compatible flash EEPROM cell with microsecond programming time for embedded memory applications

    Publication Year: 1994 , Page(s): 380 - 389
    Cited by:  Papers (14)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (948 KB)  

    This paper presents a split-gate flash EEPROM cell that relies on enhanced hot-electron injection onto the floating gate for fast 5 V-only programming. The device is referred to as the High Injection MOS (or HIMOS) cell and is fabricated in a 0.7-μm double polysilicon CMOS technology with minor additions to the standard CMOS process flow. The cell has been optimized for a virtual ground array configuration in order to shrink the area down to the range of 10-20 μm2 per bit. An extensive study is presented of the influence of applied programming voltages and device geometry on cell performance. It is shown that, for a cell area of 16.5 μm2, microsecond programming can be achieved with a program-gate voltage of 12 V and 5 V-only operation. Furthermore, during programming the unique features of the HIMOS cell result in very low drain current (approximately 25 μA per cell for 5 V-only operation) and a correspondingly low power consumption. It is shown experimentally that the combination of high programming efficiency with low power consumption indicates that 3.3 V-only operation is already viable in 0.7-μm technology. In addition, a detailed study of the various possible disturb effects confirms the reliability of the HIMOS technology, and the feasibility of using a virtual ground array for this memory cell View full abstract»

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  • Enhanced solder alloy performance by magnetic dispersions

    Publication Year: 1994 , Page(s): 452 - 457
    Cited by:  Papers (2)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    New Pb-free solder alloys with improved resistance to deformation and creep have been developed by dispersion hardening with essentially noncoarsening particles. Application of a magnetic field to molten solders containing fine (<2 μm) ferromagnetic particles led to microstructures with a uniformly distributed, three-dimensional network of the dispersoid particles. Magnetostatic repulsion among columnar chain of spheres and the formation of a network structure overwhelms the gravity effect and prevents the commonly encountered problems of particle agglomeration and segregation caused by nonwetting and density differences between the dispersoids and the molten solder matrix. The presence of the dispersoid particles makes the plastic deformation of the solder material more difficult, thus improving the strength and reducing the creep rate at elevated temperatures. A finer solidification microstructure also results from the dispersion. A magnetically processed Sn-2.5% Fe composite solder exhibited an ultimate tensile strength ~60-100% higher than the dispersion-free solder materials and, more importantly, a 20-fold improvement in creep resistance at 100°C. The presence of magnetically dispersed Fe particles in a Bi-43% Sn eutectic solder under the same high temperature conditions resulted in a five-fold increase in creep resistance View full abstract»

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  • Thermal rating characteristics of UHF power capacitors

    Publication Year: 1994 , Page(s): 348 - 353
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    The demands of miniaturization and high reliability of capacitors are interrelated with the characteristic physical parameters of its dielectric, electrode, and termination material constituents. The same parameters determine the thermal design and rating of a capacitor. Equally important, the circuit designer requires well-defined component data on power rating, heat dissipation, temperature, voltage, and current ratings. For the correct choice of components the supply of comprehensive information is expected from the capacitor manufacturer. While the evaluation of components in their real-life mounting and thermal conditions of system environment is beyond the scope of manufacturers' inspection, valuable information may be gained from the dielectric loss-frequency characteristics of the capacitors. Thermal ratings for both thick- and thin-film dielectric single-and multi-layer capacitors were evaluated using ESR-frequency characteristics and calculated conditions of thermal equilibrium. The methods of evaluation and its results are shown for a number of types of multilayer porcelain capacitors View full abstract»

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  • Higher density using diffusion patterned vias and fine-line printing

    Publication Year: 1994 , Page(s): 485 - 489
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    This paper discusses design guidelines, process steps, and test results from fabricating two 40-mm MCM-Cs using the latest thick film materials and printing techniques. The two line interface controller (LIC) modules have been designed with two large ASIC's (plus memory) and prototyped using thick film gold conductors with 3-mil line/space and 6-mil via criteria. The second prototype of the LIC module utilized silver conductors at 5-mil line and gap to further reduce cost. The second module design is using more bare die (field programmable gate arrays and memory) for a much higher interconnect density but is still using existing design guidelines. It is believed that 4-mil vias are achievable in production and will be developed for future designs requiring higher density. Diffusion patterning allows a 50% reduction (4-6 mil) in via size versus traditional printed vias (10-20 mil). In combination with fine-line printing, higher interconnect density is achievable than with conventional thick film processing. Fine-line printing improvements are a result of selecting state of the art meshes and emulsions in combination with special preparations, allowing unusually good track width reduction and excellent line definition View full abstract»

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  • Ceramic multicomponent modules: a new approach to miniaturization

    Publication Year: 1994 , Page(s): 334 - 337
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    The demand for increasing miniaturization of electronic systems enforces component manufacturers to develop new generations of small-sized components to cope with the required high component density. Reducing the size of individual components beyond the 0402 size seems not to be the best solution, as further miniaturization is limited by interconnection and placement requirements. In the design of ceramic multicomponent modules (CMM's), a different approach is followed. Employing well-accepted technologies, based on a high quality ceramic multilayer technology and thick- (or thin-) film resistor networks, customer specific modules are realized through the integration of capacitors and resistors into a single ceramic module. In addition, active elements can be mounted on top. In this way a high density of (passive) functions can be obtained in an easy mountable package. The CMM concept will be explained. In addition, the possibilities for miniaturization are addressed. Furthermore, the aspect of interconnecting the CMM to the printed circuit board (PCB) is discussed View full abstract»

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  • A multilayer ceramic series-connected capacitive-resistive device for impedance matching of high-frequency digital signal buses

    Publication Year: 1994 , Page(s): 354 - 358
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    As clock frequencies increase on digital equipment data buses, signal paths behave more like microwave striplines. It becomes ever more important to maintain bus impedance to prevent mismatches which can result in problems with false data and radiated noise. Series capacitors and resistors perform this function, Demands of miniaturization and improved manufacturing efficiency make a composite capacitor-resistor functional device attractive to designers. This paper describes the application in detail, and summarizes the development of such a composite device. Performance is compared to discrete devices in the same application. Future plans for expansion of the product series are described View full abstract»

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  • UV curable coatings for electronic components

    Publication Year: 1994 , Page(s): 326 - 333
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    Military electronic components demand the highest reliability when applied to extreme environmental conditions. Demands placed upon component manufacturers are equally suitable to the consumer market. The most stringent military test to pass is the component's durability to withstand high temperatures concomitant with high humidities. Before designing a conformal coating for capacitors and resisters, a number of thin films were cast, cured and tested at 85°C, 95% RH. The films were heat-cured silicones, epoxies, and ethoxy monomers, and UV-cured acrylated silicones, epoxies, and monomers. Acrylated polymers are free radical curing mechanisms. In this instance, free radicals were generated using UV light. The curing took place in seconds. Vapor transmission across a thin barrier film of these materials was measured to determine the film's integrity in withstanding simultaneously high temperatures and humidities. A number of correlations were discovered in regard to the chemistry needed to enhance a film's resistance to environmental conditions. There are a number of chemical reactions that take place within the film's structure when exposed to water. However, in the absence of chemical reactions, a film's integrity is related to its crosslink density and steric hinderance. The author investigated a number of heat-cured and UV-cured chemistries. In correlating vapor transmission data with a components electrical properties, solid tantalum capacitors were coated with ethoxylated epoxy and acrylated epoxy. Vapor transmission data strongly agreed with the electrical properties of a capacitor when subjected to 85°C, 95% RH. Surprisingly the electrical properties were better for the high crosslinked, steric, acrylated epoxy. Rapid cure played a major role in the film's integrity to crosslink uniformly without gas egression or pinholes. The electrical values were consistent with the vapor transmission data View full abstract»

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  • 1/f noise and its coherence as a diagnostic tool for quality assessment of potentiometers

    Publication Year: 1994 , Page(s): 436 - 445
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (708 KB)  

    The excess noise of different types of potentiometers has been investigated, and all showed a 1/f noise power-spectral density. Two types of conductive tracks are considered: carbon black resin type and metal-oxide glass cermet type. Also considered are different types of sliders: 1) metal-point contacts, 2) metal-line contacts and multiple-finger contacts, and 3) carbon brush contacts. The contributions of the end contacts, the stationary wiper (movable) contact, and the track have been investigated. The resistance and the noise of the stationary wiper contact are constriction dominated. Two different biasing conditions are proposed to measure either the coherence between current fluctuations or between voltage fluctuations in a potentiometer. The coherence measurement can serve as a fast diagnostic tool for the noise characterization and the quality of the movable contact in a potentiometer. Physical models are proposed to explain experimentally observed trends. Potentiometer 1/f noise is due to contact noise between grains in the track View full abstract»

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  • MNOS memory technology with oxynitride thin films

    Publication Year: 1994 , Page(s): 367 - 372
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    Memory properties of a metal-oxynitride-oxide-silicon (MNOS) device were investigated as a function of amount of oxygen and hydrogen impurities in the oxynitride films. The retention and endurance device characteristics improved by 60% and 107 to 108 cycles, respectively, as 13% oxygen was introduced in the oxynitride film. The interface state density decreased from 5.1 to 3.65×10 11 cm-2 eV-1, with an increase of approximately 21% oxygen in the oxynitride film, and further decreased to 2.1×1011 cm2 eV6-1 after hydrogen annealing. The results indicate that the nonvolatile memory properties of MNOS devices can be altered and considerably improved by incorporating oxygen in the oxynitride film and selecting appropriate processing and annealing conditions View full abstract»

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  • A fully integrated planar toroidal inductor with a micromachined nickel-iron magnetic bar

    Publication Year: 1994 , Page(s): 463 - 469
    Cited by:  Papers (18)  |  Patents (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    A fully integrated toroidal inductor is realized on a silicon wafer by using a multilevel metallization technique to fabricate a wrapped coil wound around a micromachined bar of high-permeability magnetic material. In particular, efforts are made to minimize the coil resistance by using thick conductor lines and electroplated vias. In this structure, a 30 μm thick nickel-iron permalloy magnetic core is wrapped with 40 μm thick multilevel copper conductor lines, constructing a conventional toroidal inductor in planar shape. A closed magnetic circuit (i.e., toroidal) in this inductive component is adopted, where magnetic core bar and wrapped conductor lines are tightly interlinked, so that leakage flux and electromagnetic interference are minimized. For an inductor size of 4 mm×1 mm×130 μm thickness having 33 turns of multilevel coils, the achieved inductance is approximately 0.4-0.1 μH at 1 kHz-1 MHz, corresponding to a core permeability of approximately 800. The measured dc resistance of the conductor lines is approximately 0.3 Ω. Since this inductive component shows favorable magnetic characteristics as well as electrical properties, it is potentially very useful as a basic inductive component in applications for magnetic microsensors, microactuators, and micromagnetic power devices such as a dc/dc converter View full abstract»

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  • Designing a reliability demonstration test on a lithography expose tool using Bayesian techniques

    Publication Year: 1994 , Page(s): 458 - 462
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    Once a wafer fabrication processing tool has demonstrated its potential for meeting process specifications, the focus of tool development broadens to include an assessment of the tool's ability to deliver the specified process repeatedly and reliably over time. Process stability and equipment reliability are assessed in a reliability demonstration test, termed a “marathon” in the SEMATECH Qualification Plan. Statistics plays a role in the design and interpretation of such testing by supplying the means for 1) specifying test length using the stated reliability goal and prior data on similar tools, and 2) constructing a confidence interval for the estimate of reliability resulting from the test. The design and analysis of a marathon test for a world-class lithography expose tool will be used as an illustration of how statistical methods can be used to advantage in assessing the reliability of a complex system. Most marathon tests conducted at SEMATECH require test times of 500 h or more, resulting in significant test costs. The motivation to reduce test costs without increasing the risk of an incorrect decision is strong. One promising approach to reducing test costs is to incorporate prior equipment performance explicitly in the design of a reliability demonstration test. Previous history and data are usually available from suppliers or users of the equipment to be tested. This paper describes our efforts to reduce test costs for a SEMATECH-sponsored lithography expose tool development project by incorporating past history into the planning of a reliability demonstration test. The statistical method used in this example has been discussed extensively in the statistical literature as a Bayesian application, but it is not widely known to equipment development engineers View full abstract»

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  • Thermal component models for electrothermal network simulation

    Publication Year: 1994 , Page(s): 413 - 424
    Cited by:  Papers (37)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1108 KB)  

    A procedure is given for developing thermal component models for electrothermal network simulation. In the new electrothermal network simulation methodology, the simulator solves for the temperature distribution within the semiconductor devices, packages, and heat sinks (thermal network) as well as the currents and voltages within the electrical network. The thermal network is represented as an interconnection of compact thermal component models so that the system designer can readily interchange different thermal components and examine different configurations of the thermal network. To facilitate electrothermal network design, the interconnection of the thermal component models is specified by the user in the same way that the interconnection of the electrical network components is specified. The thermal component models are also parameterized in terms of structural and material parameters so that the details of the heat transport physics are transparent to the user. Examples of electrothermal network simulations are given, and the temperature measurement methods used to validate the thermal component models are described View full abstract»

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  • Design and scaling of a SONOS multidielectric device for nonvolatile memory applications

    Publication Year: 1994 , Page(s): 390 - 397
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    The evolution of high-density EEPROM's continually imposes a demand on reducing power consumption while improving data retention and endurance. To meet these demands, we propose a scalable multidielectric nonvolatile memory technology where the data storage is in the form of charge trapping within the oxide-nitride-oxide (ONO) gate dielectric. This technology, called SONGS (polysilicon-blocking oxide-silicon nitride-tunnel oxide-silicon), has demonstrated remarkable scalability in programming voltage. To determine our scaling guidelines, we have developed an analytical model for the transient characteristics that examines the influence of the dielectric composition and programming voltage on programming speed. These guidelines have resulted in a scaled SONGS nonvolatile memory device that has demonstrated 8-9 V programmability with an extension towards 5 V and can be used as an ideal candidate for semiconductor disk, NVRAM, and neural network applications View full abstract»

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  • Form and capacitance of parallel-plate capacitors

    Publication Year: 1994 , Page(s): 477 - 484
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    In basic electrostatics, the formula for the capacitance of parallel-plate capacitors is derived, for the case that the spacing between the electrodes is very small compared to the length or width of the plates. However, when the separation is wide, the formula for very small separation does not provide accurate results. In our previously published papers, we used the boundary element method (BEM) to derive formulas for the capacitance of strip and disk capacitors that are applicable even when the separation is large. In this paper, we present results and formulas for the capacitances of square and rectangular capacitors View full abstract»

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  • 1-Mb memory chip using giant magnetoresistive memory cells

    Publication Year: 1994 , Page(s): 373 - 379
    Cited by:  Papers (7)  |  Patents (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    A 1-Mb nonvolatile, nondestructive readout M-R memory chip using elements with Giant Magnetoresistance Ratio (GMR) material has been designed. The chip employs dual redundancy, CMOS drive electronics with minimum gate lengths of 0.8 microns, two metal layers, and a 5-V ±10% power supply. The layout has an area of 0.9 cm sq, and approximately 50% of the chip area is devoted to the memory cell array. The memory chip is designed around 1.4 μm×6.1 μm, 80-Ω elements using GMR material; the elements are spaced 1.4 μm apart. The material is composed of two 50-Å ternary alloy layers separated by 30 Å of copper and has a nominal M-R coefficient of 6.0%. Minimum read signal is ±2.5 mV; sense current is 2.5 mA; work current is ±30 mA; and input and output is 4b wide. The memory employs a new read scheme in which two-phase sensing is employed. The scheme provides a sensitive, stable output and diminishes the array area by a factor of two, at the expense of read access time. The design contains over 700000 transistors and over 2 million memory cells; a prototype 64 K section of this design has been built, but the full design has yet to be constructed on silicon. The design demonstrates that with GMR memory cells, M-R memories can be designed with densities and speeds comparable to dynamic RAM's View full abstract»

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  • The model of interaction between arc and AgMeO contact materials

    Publication Year: 1994 , Page(s): 490 - 494
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    Based on switching experiments with cylindrical contacts of different diameters by high-speed camera observations and SEM micrographs, the effects of phase change, viscosity, and surface tension on erosion losses of AgMeO contact materials are analysed during arcing in the current range up to 1000 A rms. The erosion model of AgMeO is used for expressing the heat-force function during arc-electrode interaction and the liquid-solid, liquid-gas boundary corresponding to upper and lower erosion limits, respectively, for the reason that erosion is composed of two modes: evaporation and minute molten droplets losses. Furthermore, supposing the arc column is a hypothetical point heat source in middle of the gap, a new erosion mathematical model is established by finite differential method, and the results coincide well with those of experiments View full abstract»

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  • Test chips, test systems, and thermal test data for multichip modules in the ESPRIT-APACHIP project

    Publication Year: 1994 , Page(s): 425 - 435
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1128 KB)  

    This paper presents details of four multichip module cooling techniques using common test chips and test methods in the ESPRIT Project 2075, APACHIP. The project was concerned with the development of technology and manufacturing capabilities for single-chip packages and multichip modules. The paper presents descriptions and test results of cooling techniques investigated for multichip modules. These include heat pipes (Bull), immersion in inert fluid (GEC-Marconi), water-cooled thin membrane (GEC-Marconi), and direct-chip on water-cooled cold plate (Siemens Nixdorf Informationssysteme AG). Two 12 mm square thermal test chips are described that have been developed (NMRC) for characterization of thermal demonstrators. Test systems, established at four partner sites for diode temperature sensor calibration and thermal characterization of demonstrators, are described and compared. Statistical errors amounted to less than ±1%. Systematic errors were less than ±10%. The thermal rest data have enabled the project partners to compare the various cooling methods in terms of current and future system designs and to make decisions as to which system is most appropriate from both a technical and an economic viewpoint View full abstract»

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  • Ultra-high impact resistant digital data recorder for missile flight testing

    Publication Year: 1994 , Page(s): 398 - 403
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    A practical alternative to telemetry is being used during the flight testing of a new autonomous antitank munition for the capture of onboard test data. A unique crash-proof solid state flight data recorder (FDR) using nonvolatile flash EPROM memory was developed and extensively tested and has been successfully used on five full system flight tests to date. The FDR stores over 20 megabytes of flight data in the tactical missile's warhead volume and retains all data even after a highspeed impact with steel armor plating. Serial digital data from the missile's onboard processor and various onboard sensors is captured at a rate greater than 6 Mb/s View full abstract»

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  • Thermal performance of an integral immersion cooled multichip module package

    Publication Year: 1994 , Page(s): 405 - 412
    Cited by:  Papers (1)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB)  

    A multichip module (MCM) package was constructed that uses integral immersion cooling to transfer heat from the chips to a final heat transfer medium outside the package. The package is a miniature immersion cooled system with a pin-fin condenser that can be operated in either the submerged or vapor-space condensing mode. Sixteen chips were bonded on a 57-mm-square alumina substrate carrying copper/polyimide thin-film interconnect. Tests of the thermal performance of the system show that it is capable of handling over 160 W power with chip thermal resistances, based on chip area, as low as 2 K-cm2/watt provided by the immersion cooled portion of the thermal path. Tests have been performed with the module fully powered and with subsets of the chips powered. The results indicate that the heat transfer coefficient is similar in all partially powered modes. Data taken with condenser temperatures ranging from 20°C to 50°C were used to obtain a performance map delineating the heat transfer regimes in the module and the limits imposed by critical heat flux and condenser performance. The fluid used in the module enclosure was Fluorinert FC72 View full abstract»

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  • Performance of thin-film chip resistors

    Publication Year: 1994 , Page(s): 359 - 365
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (540 KB)  

    Increased use of thin-film surface mount chip resisters in military and high-performance industrial equipment has led to an increased awareness of potential failure modes in harsh environments. In this work, we have studied the behavior of chip resistors fabricated from tantalum nitride and nichrome metal films under biased humidity and have measured widely different results attributable to the metal film, and protective system. The effects of electrostatic discharge (ESD) and high-temperature stability on these small resistive devices was also examined and related to the resistor design View full abstract»

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  • A new reliability test for multilayer ceramic capacitors

    Publication Year: 1994 , Page(s): 344 - 347
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    Several reliability problems related to insulation resistance (IR) have been reported by multilayer ceramic capacitor ((MLC) users over the years: IR degradation over time at less than rated voltage (low voltage leakage), unsteady dissipation factor with bias applied, partial recovery of IR after repeated application of high voltage, and IR degradation of MLC's taken from sealed bags in inventory. Current test procedures, as in Mil-C-55681, designed to replicate the particular conditions related to MLC failure cannot effectively separate the root causes of these failures because causal mechanisms are confounded. Although in their entirety they do effectively expose weak lots, their application to commercial lots is cost prohibitive. An alternate test procedure designed to rapidly, effectively, and economically detect the separate root causes of MLC failures is presented. The test procedure focuses on finding the causal defects rather than attempting to reproduce and measure the individual failure mechanisms themselves. An analog megohmmeter and an oven or hot plate are the only equipment necessary for conducting the procedure, making it a good tool for users as well as capacitor suppliers. The premise that electrical stress and thermal stress on MLC's are linearly independent, and therefore separable, is presented. The separable effects of steady-state voltage and thermal/mechanical stress are applied to the study of MLC failures in this paper. Data are presented comparing the effectiveness of the test procedure to 25°C bias voltage testing, conventional voltage conditioning, and highly accelerated life test (HALT) View full abstract»

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  • Computer-aided design of passive multilayer components using electromagnetic field computation

    Publication Year: 1994 , Page(s): 338 - 343
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    A new approach for computer-aided design of passive multilayer components is presented. By means of electromagnetic field computation with the finite element method, the characteristic electric and magnetic parameters of the components such as resistance, capacitance, and inductance are calculated. The employed electromagnetic formulations are presented, as well as a brief description of the numerical method. After resuming specific multilayer component's characteristics, the design method is applied to a low capacitance value, high-frequency ceramic chip capacitor and to an RC-filter with bandpass characteristics. Obtained results are compared to measured quantities in order to show the accuracy and the capability of the presented method View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope