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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 3 • Date Sept. 1994

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Displaying Results 1 - 14 of 14
  • A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation

    Publication Year: 1994, Page(s):343 - 353
    Cited by:  Papers (10)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1384 KB)

    A new, parallel, nearest-neighbor (NN) pattern classifier, based on a 2D Cellular Automaton (CA) architecture, is presented in this paper. The proposed classifier is both time and space efficient, when compared with already existing NN classifiers, since it does not require complex distance calculations and ordering of distances, and storage requirements are kept minimal since each cell stores inf... View full abstract»

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  • Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design

    Publication Year: 1994, Page(s):273 - 291
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1755 KB)

    Built-In Self Test (BIST) has been proposed as a powerful technique for addressing the highly complex testing problems of VLSI circuits. In the BIST methodology, two major problems which must be addressed are test generation and response analysis. In this paper, we present an efficient unified procedure, named three-phase cluster partitioning, to automatically synthesize a pseudo-exhaustive test g... View full abstract»

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  • Design of a pipelined datapath synthesis system for digital signal processing

    Publication Year: 1994, Page(s):292 - 303
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1122 KB)

    In this paper, we describe the design of SODAS-DSP (Sogang Design Automation System-DSP), a pipelined datapath synthesis system targeted for application-specific DSP chip design. Through facilitated user interaction, the design space of pipelined datapaths for given design descriptions can be explored to produce an optimal design which meets design constraints. Taking SFG (Signal Flow Graph) in sc... View full abstract»

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  • Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures

    Publication Year: 1994, Page(s):304 - 311
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (941 KB)

    The growing trend towards VLSI implementation of crucial tasks in critical applications has increased both the demand for and the scope of fault-tolerant VLSI systems. In this paper, we present a self-recovering microarchitecture synthesis system. In a self-recovering microarchitecture, intermediate results are compared at regular intervals, and if correct saved in registers (checkpointing). On th... View full abstract»

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  • A fault-tolerant permutation network modulo arithmetic processor

    Publication Year: 1994, Page(s):312 - 319
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (841 KB)

    Conventional fault-tolerant modulo arithmetic processors rely on the properties of a residue number system with L redundant moduli to detect up to L/2 errors. In this paper, we propose a new scheme that combines r-out-of-s residue codes with Berger codes to concurrently detect any number of module errors without any redundant moduli. In addition, this scheme can tolerate L faults if L redundant mo... View full abstract»

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  • Logic design error diagnosis and correction

    Publication Year: 1994, Page(s):320 - 332
    Cited by:  Papers (15)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1286 KB)

    Logic verification tools are often used to verify a gate-level implementation of a digital system in terms of its functional specification. If the implementation is found not to be functionally equivalent to the specification, it is important to correct the implementation automatically. This paper describes a formal method for the diagnosis and correction of logic design errors in an incorrect gat... View full abstract»

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  • Certified timing verification and the transition delay of a logic circuit

    Publication Year: 1994, Page(s):333 - 342
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1089 KB)

    Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transi... View full abstract»

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  • Loop based design for wafer scale systems

    Publication Year: 1994, Page(s):354 - 357
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (434 KB)

    This paper presents a loop based design scheme suitable for wafer scale systems and introduces a variant of the basic reconfiguration algorithm. The underlying topology has been extended to a nonplanar graph of vertex degree five. The yield for this system is higher than that of a planar graph of vertex degree six and requires less hardware for its implementation. Several comparisons among various... View full abstract»

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  • Determining objective functions in systolic array designs

    Publication Year: 1994, Page(s):357 - 360
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (414 KB)

    The space-time mapping of the dependency matrix of an algorithm may be used to study proposed systolic array implementations. In this paper we consider nested loop structures and use the space-time mapping approach to examine six objective functions, processor pipelining rate, computation time, throughput, number of processing elements, geometric area and space utilization. An elementary expressio... View full abstract»

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  • A VLSI architecture for a real-time code book generator and encoder of a vector quantizer

    Publication Year: 1994, Page(s):360 - 364
    Cited by:  Papers (18)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (438 KB)

    Image compression applications use vector quantization (VQ) for its high compression ratio and image quality. The current VQ hardware employs static instead of dynamic code book generation as the latter demands intensive computation and corresponding expensive hardware even though it offers better image quality. This paper describes a VLSI architecture for a real-time dynamic code book generator a... View full abstract»

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  • Field programmable gate arrays and floating point arithmetic

    Publication Year: 1994, Page(s):365 - 367
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (321 KB)

    We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various feat... View full abstract»

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  • On broad-side delay test

    Publication Year: 1994, Page(s):368 - 372
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (565 KB)

    A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit's response to this first vector. This delay test form is called "broad-side" since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on... View full abstract»

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  • A low latency asynchronous arbitration circuit

    Publication Year: 1994, Page(s):372 - 377
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (686 KB)

    We present an asynchronous circuit for an arbiter cell that can be used to construct cascaded multiway arbitration circuits. The circuit is completely speed-independent. It has a short response delay at the input request-grant handshake link due to both a) the propagation of requests in parallel with starting arbitration and b) the concurrent resetting of request-grant handshakes in different casc... View full abstract»

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  • Power-delay characteristics of CMOS adders

    Publication Year: 1994, Page(s):377 - 381
    Cited by:  Papers (27)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (487 KB)

    An approach to designing CMOS adders for both high speed and low power is presented by analyzing the performance of three types of adders - linear time adders, logN time adders and constant time adders. The representative adders used are a ripple carry adder, a blocked carry lookahead adder and several signed-digit adders, respectively. Some of the tradeoffs that are possible during the logic desi... View full abstract»

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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu