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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 22 of 22

Publication Year: 2016, Page(s):C1 - C4
| PDF (416 KB)
• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2016, Page(s): C2
| PDF (88 KB)
• ### Defect- and Variation-Tolerant Logic Mapping in Nanocrossbar Using Bipartite Matching and Memetic Algorithm

Publication Year: 2016, Page(s):2813 - 2826
| | PDF (4086 KB) | HTML

High defect density and extreme parameter variation make it very difficult to implement reliable logic functions in crossbar-based nanoarchitectures. It is a major design challenge to tolerate defects and variations simultaneously for such architectures. In this paper, a method based on a bipartite matching and memetic algorithm is proposed for defect- and variation-tolerant logic mapping (D/VTLM)... View full abstract»

• ### Detector for MLC NAND Flash Memory Using Neighbor-A-Priori Information

Publication Year: 2016, Page(s):2827 - 2836
Cited by:  Papers (2)
| | PDF (2812 KB) | HTML

Cell-to-cell interference (CCI), arising from parasitic coupling-capacitance between adjacent cells, is a major factor for the degradation of cell threshold voltage in today's flash memory chips. In this paper, three novel postprocessing detection schemes that exploit the a priori information of neighboring/interfering cells for mitigating the CCI effect in multilevel cell NAND flash memory are pr... View full abstract»

• ### Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive Control

Publication Year: 2016, Page(s):2837 - 2850
Cited by:  Papers (2)
| | PDF (3636 KB) | HTML

Internet-of-Things architecture aims to provide smart connectivity not only with existing computers, but also with new context-aware computing resources, extending soon beyond von Neumann devices for the purpose of mining, prediction, and control of cyber and physical components. These cyber-physical systems (CPSs) not only lead to the accumulation of large amounts of data that can be used to buil... View full abstract»

• ### Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM

Publication Year: 2016, Page(s):2851 - 2860
Cited by:  Papers (2)
| | PDF (2454 KB) | HTML

As the technology node scales down, the spin-transfer-torque random access memory (STT-RAM) has been considered as a promising memory solution owing to its scalability. However, the increased process variation and the reduced supply voltage lead to degradation in the sensing yield (SY) as well as an increase in the read disturbance probability. Temperature variation further aggravates this phenome... View full abstract»

• ### Magnetic Domain-Wall Racetrack Memory-Based Nonvolatile Logic for Low-Power Computing and Fast Run-Time-Reconfiguration

Publication Year: 2016, Page(s):2861 - 2872
Cited by:  Papers (2)
| | PDF (2749 KB) | HTML

The high power and the long global interconnect delay are two of the major bottlenecks that limit the further scaling down of the process nodes in the VLSI systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and the interconnect delay. Current-induced magnetic domain-wall (DW) racetrack memory (RM) has the advantages of nonv... View full abstract»

• ### Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Publication Year: 2016, Page(s):2873 - 2886
Cited by:  Papers (2)
| | PDF (3185 KB) | HTML

In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementin... View full abstract»

• ### A 0.25–3.25-GHz Wideband CMOS-RF Spectrum Sensor for Narrowband Energy Detection

Publication Year: 2016, Page(s):2887 - 2898
Cited by:  Papers (2)
| | PDF (5105 KB) | HTML

A wideband spectrum sensing system for cognitive radio is designed and implemented in a 130-nm radio frequency mixed-mode CMOS technology. The system employs an I-Q downconverter, a pair of complex filters, and a pair of envelope detectors to perform the spectrum sensing from 250 MHz to 3.25 GHz. The design makes use of the bandpass nature of the complex filter to achieve two objectives: 1) separa... View full abstract»

• ### A Statistical Design Approach for a Digitally Programmable Mismatch-Tolerant High-Speed Nauta Structure Differential OTA in 65-nm CMOS

Publication Year: 2016, Page(s):2899 - 2910
Cited by:  Papers (2)
| | PDF (3447 KB) | HTML

The Nauta structure differential operational transconductance amplifier (OTA) is introduced as a solution to an amplifier design in deep submicrometer CMOS. This simple high-speed inverter-based architecture uses a negative conductance dc gain enhancement technique to produce high dc gains and large unity gain frequencies. The design tradeoff is that the achievable dc gain is proportional to trans... View full abstract»

• ### A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time $Sigma$ – $Delta$ ADC

Publication Year: 2016, Page(s):2911 - 2917
| | PDF (2104 KB) | HTML

Inverter-based implementation of operational-transconductance amplifiers is an attractive approach for low-voltage realization of analog subsystems. However, the high sensitivity of inverterlike amplifiers' performance to process and temperature variations limit the achievable performance of the whole system across process and temperature corners. In this paper, a tuning technique is proposed to m... View full abstract»

• ### Digitally Assisted Built-In Tuning Using Hamming Distance Proportional Signatures in RF Circuits

Publication Year: 2016, Page(s):2918 - 2931
| | PDF (3119 KB) | HTML

In this paper, a novel built-in tuning technique to compensate for process variability-induced imperfections in RF circuits is proposed. The yield improvement methodology proposed is a generic and self-contained tuning method that does not require a digital signal processor as in prior software-based methods or the use of a tester. The technique uses digital logic that can be synthesized on-chip a... View full abstract»

• ### Efficient Architecture for Soft-Input Soft-Output Sphere Detection With Perfect Node Enumeration

Publication Year: 2016, Page(s):2932 - 2945
Cited by:  Papers (4)
| | PDF (3169 KB) | HTML

The application of the turbo principle allows to exploit the full potential of multiple-input multiple-output (MIMO) communications at the cost of increasing the computational effort at the receiver. In the context of soft-input soft-output tree search detection, the computation of metric values and the optimal node order represents two of the most computationally demanding operations. Heuristic a... View full abstract»

• ### Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach

Publication Year: 2016, Page(s):2946 - 2959
Cited by:  Papers (7)
| | PDF (3150 KB) | HTML

Trustworthiness of system-on-chip designs is undermined by malicious logic (Trojans) in third-party intellectual properties (3PIPs). In this paper, duplication, diversity, and isolation principles have been extended to detect build trustworthy systems using untrusted, potentially Trojan-infected 3PIPs. We use a diverse set of vendors to prevent collusions between the 3PIPs from the same vendor. We... View full abstract»

• ### A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode- Controlled Switching Regulators

Publication Year: 2016, Page(s):2960 - 2969
| | PDF (4388 KB) | HTML

This paper describes a one-pin mode transition circuit that addresses the issues related to clock synchronization in switching regulators during the mode transitions between external timing resistor and external clock. The proposed circuit reduces the circuit complexity needed to achieve mode transition during synchronization by utilizing switched-capacitor and sampling design techniques. It linea... View full abstract»

• ### A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads

Publication Year: 2016, Page(s):2970 - 2982
Cited by:  Papers (7)
| | PDF (4925 KB) | HTML

This paper presents an on-chip, low drop-out (LDO) voltage regulator with improved power-supply rejection (PSR) able to drive large capacitive loads. The LDO compensation is achieved via a custom, wide bandwidth capacitance multiplier (c-multiplier) that emulates a nanofarad-range capacitance at the LDO output node. The LDO frequency response resembles that of externally compensated LDOs, leading ... View full abstract»

• ### A 10- $mu text{s}$ Transient Recovery Time Low-EMI DC-DC Buck Converter With $Delta$ – $Sigma$ Modulator

Publication Year: 2016, Page(s):2983 - 2992
Cited by:  Papers (1)
| | PDF (3397 KB) | HTML

This paper presents a 10-μs transient recovery time and a low electromagnetic interference dc-dc buck converter with a second-order delta-sigma (Δ-Σ) modulator. The proposed buck converter employs the techniques of oversampling, noise shaping, fast-transient path, mode selector, and second-order Δ-Σ modulator to achieve spur reduction and to improve transient rec... View full abstract»

• ### Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM

Publication Year: 2016, Page(s):2993 - 2997
Cited by:  Papers (2)
| | PDF (1100 KB) | HTML

Spin-transfer-torque random access memory (STT-RAM) has attracted much research interest because of its characteristics of nonvolatility (i.e., zero standby power) and small cell size (i.e., high density and high performance). As the technology node is scaled down, however, the sensing margin of the STT-RAM is degraded because of the increased process variation and reduced supply voltage. To impro... View full abstract»

Publication Year: 2016, Page(s):2998 - 3002
| | PDF (1367 KB) | HTML

The NAND flash memory has been widely used in computer and consumer electronic devices. A multilevel-cell (MLC) NAND flash memory allows two or more bits to be stored per cell, improving the cell density and, hence, reducing the cost. The lower price of the MLC NAND has made it appearing in both consumer product and datacenter markets. In MLC NAND, the page read latency varies according to the pag... View full abstract»

• ### Multiplierless Unity-Gain SDF FFTs

Publication Year: 2016, Page(s):3003 - 3007
Cited by:  Papers (2)
| | PDF (1284 KB) | HTML

In this brief, we propose a novel approach to implement multiplierless unity-gain single-delay feedback fast Fourier transforms (FFTs). Previous methods achieve unity-gain FFTs by using either complex multipliers or nonunity-gain rotators with additional scaling compensation. Conversely, this brief proposes unity-gain FFTs without compensation circuits, even when using nonunity-gain rotators. This... View full abstract»

Publication Year: 2016, Page(s):3008 - 3012
Cited by:  Papers (3)
| | PDF (1923 KB) | HTML

Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processors, an efficient addressing scheme for FFT data as well as twiddle factors is required. The signal flow graph of SRFFT is the same as radix-2 FFT, and therefore, th... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2016, Page(s): C3
| PDF (178 KB)

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu