# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Displaying Results 1 - 22 of 22

Publication Year: 2016, Page(s): C1
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2016, Page(s): C2
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• ### A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity

Publication Year: 2016, Page(s):1397 - 1410
Cited by:  Papers (1)
| | PDF (1244 KB) | HTML

Charge scaling data converters include a binary-weighted capacitor array in their structure. New methods for the placement and sizing of capacitor arrays with increased ratio accuracy and improved converter linearity are presented in this paper. A new model of statistical variation is used, which takes into account both spatial correlation between devices and device area. This is combined with a n... View full abstract»

• ### On Improving the Security of Logic Locking

Publication Year: 2016, Page(s):1411 - 1424
Cited by:  Papers (3)
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Due to globalization of integrated circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware Trojans. EPIC locks the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the locked netlist, in a time linear to the number of keys, by sensitizin... View full abstract»

• ### Graceful Space Degradation: An Uneven Space Management for Flash Storage Devices

Publication Year: 2016, Page(s):1425 - 1434
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The high cell density, multilevel-cell programming, and manufacturing process variance force the new coming flash memory to have large bit-error-rate variance among blocks and pages, where a flash chip consists of multiple blocks and each block consists of a fixed number of pages. In order to avoid storing the crucial user data in more fragile pages, conventional flash management software tends to... View full abstract»

• ### Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation

Publication Year: 2016, Page(s):1435 - 1448
Cited by:  Papers (1)
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The random telegraph noise (RTN) is becoming more serious in advanced technologies. Due to the unpredictability of the physical phenomenon, RTN is a good randomness source for true random number generators (TRNG). In this paper, we build fundamental randomness models for TRNGs based on single trap- and multiple traps-induced RTN. We theoretically derive the autocorrelation coefficient, bias, and b... View full abstract»

• ### Efficient Layout Generation and Design Evaluation of Vertical Channel Devices

Publication Year: 2016, Page(s):1449 - 1460
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Vertical gate-all-around (VGAA) structure has been shown to be one of the most promising devices for the scaling beyond 10 nm for its reduced area, large driving current, and good gate control. Moreover, emerging devices such as heterojunction tunneling FETs are more amenable to vertical fabrication. However, past studies of vertical channel devices focused more on regular memory architectures and... View full abstract»

• ### Adapting $\text{B}^{+}$ -Tree for Emerging Nonvolatile Memory-Based Main Memory

Publication Year: 2016, Page(s):1461 - 1474
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Among the emerging nonvolatile memory (NVM) technologies, some resistive memories, including phase change memory (PCM), spin-transfer torque magnetic random access memory (STT-RAM), and metal-oxide resistive RAM (ReRAM), have been considered as promising replacements of conventional dynamic RAM (DRAM) to build future main memory systems. Main memory databases can benefit from their nice features, ... View full abstract»

• ### Joint Modulo Scheduling and $V_{\mathrm{ dd}}$ Assignment for Loop Mapping on Dual- $V_{\mathrm{ dd}}$ CGRAs

Publication Year: 2016, Page(s):1475 - 1488
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Coarse-grained reconfigurable architecture (CGRA) is becoming an increasingly attractive platform because of its high performance and power (or energy) efficiency. To reduce energy consumption, the dual-Vdd technique has been employed in CGRAs, and the modulo scheduling technique is widely used to improve performance of applications. To achieve both high performance and energy-efficienc... View full abstract»

• ### Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Publication Year: 2016, Page(s):1489 - 1502
Cited by:  Papers (6)
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A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementary elements to solve the continuity equation for minority carriers in the volume based on the finite-difference method. A substrate parasitic net... View full abstract»

• ### All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution

Publication Year: 2016, Page(s):1503 - 1508
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In this paper, we propose a single probability density function for the distributions of the delay in the presence of the process variation for different regions of operation. The delay variation model is inspired by considering the analytical current models for each operating region. Based on these models, we suggest using the log-skew-normal distribution for modeling the delay variation for a wi... View full abstract»

• ### Three-Port Model of a Modern MOS Transistor in Millimeter Wave Band, Considering Distributed Effects

Publication Year: 2016, Page(s):1509 - 1518
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Distributed nature of an MOS transistor becomes significant in high frequencies, especially in the millimeter wave band. Two types of distributed effects are encountered in an MOS transistor: the distributed effect along the transistor channel, referred as nonquasi static (NQS) effect, and the distributed effect along the gate finger. We denote the former as lateral distributed effect and the late... View full abstract»

• ### Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process

Publication Year: 2016, Page(s):1519 - 1531
| | PDF (2548 KB) | HTML

Self-aligned double patterning (SADP) is one of the most promising techniques for sub-20 nm technology. Spacer-is-dielectric SADP using a cut process is getting popular because of its higher design flexibility; for example, it can decompose odd cycles without the need of inserting any stitch. This paper presents the first work that applies the cut process for decomposing odd cycles during routing.... View full abstract»

• ### Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography

Publication Year: 2016, Page(s):1532 - 1545
Cited by:  Papers (1)
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As the feature size keeps scaling down and the circuit complexity increases rapidly, a more advanced hybrid lithography, which combines multiple patterning and electron-beam lithography (EBL), is promising to further enhance the pattern resolution. In this paper, we formulate the layout decomposition problem for this hybrid lithography as a minimum vertex deletion View full abstract»

• ### Built-In Self-Heating Thermal Testing of FPGAs

Publication Year: 2016, Page(s):1546 - 1556
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Field programmable gate arrays (FPGAs) are designed and fabricated using the most advanced CMOS technology nodes to meet performance and power demands. This makes them susceptible to many manufacturing and reliability challenges. Increasing chip temperature is a major reliability concern since various failure mechanisms are accelerated at high chip temperature, which require thermal-aware testing ... View full abstract»

• ### Flexibility and Optimization of QBF Skolem–Herbrand Certificates

Publication Year: 2016, Page(s):1557 - 1568
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Skolem and Herbrand functions are important certificates validating the truth and falsity, respectively, of quantified Boolean formulas (QBFs). They are essential in various synthesis and verification applications. Recent advancement established a linear time extraction of Skolem/Herbrand functions from QBF consensus/resolution proofs. However, the obtained functions are often excessively large an... View full abstract»

• ### Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells

Publication Year: 2016, Page(s):1569 - 1573
Cited by:  Papers (1)
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Conventional detailed placement algorithms typically assume all standard cells in the design have the same height. However, as the complexity and design requirement increase in modern very large-scale integration design, designs with mixed single-row height and double-row height standard cells come into existence in order to address the emerging standard cell design challenges. A detailed placemen... View full abstract»

• ### Introducing IEEE Collabratec

Publication Year: 2016, Page(s): 1574
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• ### IEEE Access

Publication Year: 2016, Page(s): 1575
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• ### Imagine a community hopeful for the future

Publication Year: 2016, Page(s): 1576
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2016, Page(s): C3
| PDF (246 KB)
• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

Publication Year: 2016, Page(s): C4
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## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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## Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu