# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 23 of 23

Publication Year: 2016, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Publication Year: 2016, Page(s): C2
| PDF (40 KB)
• ### A Low-Distortion High-Efficiency Class-D Audio Amplifier Based on Sliding Mode Control

Publication Year: 2016, Page(s):713 - 717
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This brief presents a low-power low-distortion high-efficiency class-D audio amplifier. The proposed architecture uses an integral sliding mode controller with a novel on-chip continuous current sensor. A full-bridge output stage is used to increase the output power, and an adaptive nonoverlapping-clock generation technique is presented to eliminate the short circuit current. Moreover, the switchi... View full abstract»

• ### On the Nonconvergence of the Vector Fitting Algorithm

Publication Year: 2016, Page(s):718 - 722
Cited by:  Papers (1)
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The vector fitting (VF) algorithm, as a variant of the Sanathanan-Koerner (SK) algorithm, has been widely used for frequency-domain modeling. This algorithm is essentially an iterative procedure, in which a revised linear least squares (LS) problem is solved in each step. So far, there has been hardly any analytical result in the literature on the convergence property of the SK or the VF algorithm... View full abstract»

• ### A 0.67- $\mu\text{W}$ 177-ppm/°C All-MOS Current Reference Circuit in a 0.18- $\mu\text{m}$ CMOS Technology

Publication Year: 2016, Page(s):723 - 727
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This brief describes a nanopower current reference circuit that has been fabricated in a standard 0.18-μm CMOS technology. The proposed circuit is an extension of the resistorless current reference circuit suggested by Oguey and Aebischer. This extension is a simple circuit arrangement that is capable of reducing the temperature coefficient (TC) of Oguey's circuit. The measurements have bee... View full abstract»

• ### Analysis and Design of Two-Port $N$- Path Bandpass Filters With Embedded Phase Shifting

Publication Year: 2016, Page(s):728 - 732
Cited by:  Papers (2)
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N-path switched- RC circuits are a promising solution for realizing tunable high- Q filters on chip. Here, a novel method of embedding phase-shifting functionality into the two-port N- path filter response by shifting the phase of the input and output clock sets relative to each other is introduced. Furthermore, a two-port design allows us to embed variable attenuation that can be useful in applic... View full abstract»

• ### A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector

Publication Year: 2016, Page(s):733 - 737
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This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple ... View full abstract»

• ### Innovative Theory on Multiband NGD Topology Based on Feedback-Loop Power Combiner

Publication Year: 2016, Page(s):738 - 742
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The signal delay is one of the main issues encountered during the design and fabrication of the RF/microwave electronic circuits and systems. Therefore, the correction process is constantly needed for the signal delay cancelation. This brief introduces an innovative theory of a microwave circuit topology delay suppressor. The original circuit was originally built with a passive power combiner (PWC... View full abstract»

• ### A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications

Publication Year: 2016, Page(s):743 - 747
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This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS ... View full abstract»

• ### Steady-State Analysis of Switching Converters via Frequency-Domain Circuit Equivalents

Publication Year: 2016, Page(s):748 - 752
Cited by:  Papers (1)
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This brief presents a frequency-domain approach for the steady-state analysis of pulsewidth-modulated converters and switched circuits with nonideal switching behavior. The proposed strategy generalizes recent methodologies based on the Fourier expansion of the steady-state responses of a periodically switching circuit and on the simulation of an augmented linear-time-invariant system. This system... View full abstract»

Publication Year: 2016, Page(s):753 - 757
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This brief presents a multiternary digit (trit) multiplier design in carbon-nanotube field-effect transistor (CNTFET) technology using unary operators of multivalued logic. The proposed structure is based on the classical Wallace multiplier and includes a novel ternary multiplexer design requiring only a small number of CNTFETs. Two ternary full-adder configurations are also proposed based on an e... View full abstract»

• ### A 40-Gb/s 211-1 PRBS With Distributed Clocking and a Trigger Countdown Output

Publication Year: 2016, Page(s):758 - 762
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A 211-1 pseudo-random binary sequence (PRBS) generator with trigger synchronization output (9.77-MHz rate) is implemented using synthetic transmission lines for the clock distribution. The full-rate data sequence is sourced from a 2:1 multiplex of dual shift register outputs synchronized to a half-rate clock. Quadrature half-rate clocks generated by a dual-mode (Dynastat) divide-by-2 ar... View full abstract»

• ### Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links

Publication Year: 2016, Page(s):763 - 767
| | PDF (1079 KB) | HTML Media

Asynchronous handshaken interchip links are very popular among neuromorphic full-custom chips due to their delay-insensitive and high-speed properties. Of special interest are those links that minimize bit-line transitions for power saving, such as the two-phase handshaken non-return-to-zero (NRZ) 2-of-7 protocol used in the SpiNNaker chips. Interfacing such custom chip links to field-programmable... View full abstract»

• ### Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits

Publication Year: 2016, Page(s):768 - 772
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This brief presents a high-speed inductorless D flip-flop (DFF) architecture that works on the principle of equalization using two feedbacks. Feedback from the first latch output to the input effectively results in a linear equalizer, whereas the feedback of the flip-flop output to the input culminates in decision feedback equalization. The proposed feedback-based DFF designed in a 90-nm CMOS tech... View full abstract»

• ### Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCs

Publication Year: 2016, Page(s):773 - 777
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This brief introduces a new digital postcorrection technique for calibrating time-interleaved analog-to-digital converters (ADCs). It utilizes one additional sub-ADC to resolve the performance degradation problem near the Nyquist rate that occurred in the conventional multichannel filtering approach. Time skew, gain, offset, and bandwidth mismatches as well as the sub-ADC nonlinearities are all in... View full abstract»

• ### Periodic Properties of Chebyshev Polynomial Sequences Over the Residue Ring $\mathbb{Z}/2^{k}\mathbb{Z}$

Publication Year: 2016, Page(s):778 - 782
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This brief analyzes in detail the relation of the period, the initial value, and the degree of Chebyshev polynomials over the residue ring Z/2kZ. In particular, it is demonstrated that a recently proposed public-key cryptosystem based on Chebyshev polynomials over Z/2kZ is not secure. View full abstract»

• ### A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution

Publication Year: 2016, Page(s):783 - 787
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We propose a unified methodology for converting any probability distribution which satisfies a few simple conditions to a uniformly distributed random bit stream. The proposed methodology is based on a bit truncation scheme and can be trivially implemented by basic circuit modules. A sufficient condition is derived to determine the optimal truncation. The proposed methodology is verified by three ... View full abstract»

• ### Truncated Prediction Output Feedback Control of a Class of Lipschitz Nonlinear Systems With Input Delay

Publication Year: 2016, Page(s):788 - 792
Cited by:  Papers (1)
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This brief addresses an output feedback control design for Lipschitz nonlinear systems in the presence of input delay. A nonlinear observer is introduced to estimate the system states. A truncated predictor state feedback, which is the conventional predictor state feedback law with the distributed term dropped, is implemented with the estimated states. Lyapunov-Krasovskii functionals are construct... View full abstract»

• ### An Area Time-Efficient Structure to Find the Approximate First Two Minima for Min-Sum-Based LDPC Decoders

Publication Year: 2016, Page(s):793 - 797
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Aiming at reducing the hardware complexity of low-density parity-check (LDPC) decoders based on min-sum algorithms, this brief presents a general structure to find the minimum value and an approximate second minimum value. The proposed structure is proved to obtain the exact second minimum value with high probability in theory, and simulation results demonstrate that only a negligible degradation ... View full abstract»

• ### Unbiased Finite-Memory Digital Phase-Locked Loop

Publication Year: 2016, Page(s):798 - 802
Cited by:  Papers (5)
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Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFM... View full abstract»

• ### Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths

Publication Year: 2016, Page(s):803 - 807
Cited by:  Papers (1)
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This brief presents a new algorithm optimized for radix-2 real-valued fast Fourier transform (RFFT) through rigorous formula derivation. Based on that, a novel two-parallel pipelined radix-2 RFFT architecture is proposed with only real datapaths instead of hybrid datapaths. The architecture takes advantage of saving the arithmetic resource in the time-division multiplexing approach to achieve 100%... View full abstract»

• ### Diameter-Constrained Overlays With Faulty Links: Equilibrium, Stability, and Upper Bounds

Publication Year: 2016, Page(s):808 - 812
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In network overlays, virtual links among remote processes are usually established to circumvent the limitations of underlying protocols. The resulting dynamics have been recently studied, based on a novel random graph model that assumes that no link failure can occur. In that model, the case of faulty links has been only marginally stated to stimulate future research activities. Unfortunately, net... View full abstract»

• ### IEEE Circuits and Systems Society Information

Publication Year: 2016, Page(s): C3
| PDF (34 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org