# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Displaying Results 1 - 24 of 24

Publication Year: 2016, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2016, Page(s): C2
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• ### Editorial First TVLSI Best AE and Reviewer Awards

Publication Year: 2016, Page(s): 2613
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• ### Precharge-Free, Low-Power Content-Addressable Memory

Publication Year: 2016, Page(s):2614 - 2621
Cited by:  Papers (1)
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Content-addressable memory (CAM) is the hardware for parallel lookup/search. The parallel search scheme promises a high-speed search operation but at the cost of high power consumption. Parallel NOR- and NAND-type matchline (ML) CAMs are suitable for high-search-speed and low-power-consumption applications, respectively. The NOR-type ML CAM requires high power, and therefore, the reduction of its ... View full abstract»

• ### A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

Publication Year: 2016, Page(s):2622 - 2633
Cited by:  Papers (3)
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Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical d... View full abstract»

• ### Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell

Publication Year: 2016, Page(s):2634 - 2642
Cited by:  Papers (6)
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This paper presents a Schmitt-trigger-based single-ended 11T SRAM cell, which significantly improves read and write static noise margin (SNM) and consumes low power. Simulation results show that the cell also achieves the lowest leakage power dissipation among the cells considered for comparison. We also investigate the impact of process, voltage, and temperature variations on various performance ... View full abstract»

• ### Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm

Publication Year: 2016, Page(s):2643 - 2653
Cited by:  Papers (2)
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Nonbinary LDPC codes outperform their binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node (CN) processor, for high-order Galois fields (GFs) higher than GF(16). To overcome this drawback, we propose an approximation for the trellis min-max algorithm that allows us to reduce the number of exchanged messages between th... View full abstract»

• ### Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device

Publication Year: 2016, Page(s):2654 - 2664
Cited by:  Papers (2)
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A multilevel per cell (MLC) technique significantly improves the storage density, but also poses serious data integrity challenge for NAND flash memory. This consequently makes the low-density parity-check (LDPC) code and the soft-decision memory sensing become indispensable in the next-generation flash-based solid-state storage devices. However, the use of LDPC codes inevitably increases memory r... View full abstract»

• ### Low-Power FPGA Design Using Memoization-Based Approximate Computing

Publication Year: 2016, Page(s):2665 - 2678
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Field-programmable gate arrays (FPGAs) are increasingly used as the computing platform for fast and energy-efficient execution of recognition, mining, and search applications. Approximate computing is one promising method for achieving energy efficiency. Compared with most prior works on approximate computing, which target approximate processors and arithmetic blocks, this paper presents an approx... View full abstract»

• ### Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals

Publication Year: 2016, Page(s):2679 - 2688
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In this paper, we present a low-power, efficacious, and scalable system for the detection of symptomatic patterns in biological audio signals. The digital audio recordings of various symptoms, such as cough, sneeze, and so on, are spectrally analyzed using a discrete wavelet transform. Subsequently, we use simple mathematical metrics, such as energy, quasi-average, and coastline parameter for vari... View full abstract»

• ### A Saliency-Driven LCD Power Management System

Publication Year: 2016, Page(s):2689 - 2702
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Large liquid crystal display (LCD) technology is being widely used in every corner of our modern life, ranging from personal laptops to flat-panel televisions. Among all the components in an LCD display system, the backlight panel is the dominant power consumer, irrespective of lighting technology or class. In this paper, a saliency-based field-programmable gate array accelerator for revolutionary... View full abstract»

• ### 2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D Integration

Publication Year: 2016, Page(s):2703 - 2711
Cited by:  Papers (2)
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This paper introduces a hybrid capacitive coupling interconnects (CCIs) array suitable for bumpless flip-chip 3-D integration. Inside the hybrid array, both single-ended and common-centroid differential CCIs are interleaved together to cancel the crosstalk among them. The crosstalk cancellation capability of its own allows CCIs to be placed closer and thus improves the area efficiency. A high gain... View full abstract»

• ### System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection

Publication Year: 2016, Page(s):2712 - 2725
Cited by:  Papers (5)
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Negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) are leading reliability concerns for modern microprocessors. In this paper, a framework is proposed to analyze the impact of BTI (NBTI and PBTI) and HCI on state-of-art microprocessors and to estimate microprocessor lifetimes due to each wearout mechanism. Our methodology fin... View full abstract»

• ### Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories

Publication Year: 2016, Page(s):2726 - 2734
Cited by:  Papers (1)
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Error correction code (ECC) and built-in self-repair (BISR) techniques by using redundancies have been widely used for improving the yield and reliability of embedded memories. The target faults of these two schemes are soft errors and permanent (hard) faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft errors and hard defects simultaneo... View full abstract»

• ### Reliable Power Gating With NBTI Aging Benefits

Publication Year: 2016, Page(s):2735 - 2744
Cited by:  Papers (4)
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In this paper, we show that negative bias temperature instability (NBTI) aging of sleep transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT), presents considerable benefits for power-gated circuits. Indeed, it reduces static power due to leakage current, and increases ST switch efficiency, making power gating more efficient and effective over time. The ... View full abstract»

• ### Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors

Publication Year: 2016, Page(s):2745 - 2758
Cited by:  Papers (2)
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Three-dimensional video processing has high computation requirements and multicore processors realized in 3-D integrated circuits (ICs) provide promising high performance computing platforms. However, the conventional approaches to accelerate the computations involved in 3-D video processing do not exploit the high performance potential of 3-D ICs. In this paper, we propose an application-driven m... View full abstract»

• ### A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis

Publication Year: 2016, Page(s):2759 - 2767
Cited by:  Papers (3)
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Procedures that were described earlier increase the accuracy of defect diagnosis by ignoring small subsets of tests in order to produce smaller candidate fault sets. The premise behind these procedures is that most of the tests in a given test set are useful for defect diagnosis, and only small numbers of tests need to be ignored. This paper makes the new observation that it is possible to use sma... View full abstract»

• ### A $4\times 5$ -Gb/s 1.12- $\mu \text{s}$ Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels

Publication Year: 2016, Page(s):2768 - 2777
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A 4×5-Gb/s reference-less receiver is proposed in a 0.13-μm CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded fr... View full abstract»

• ### Noise Coupling Models in Heterogeneous 3-D ICs

Publication Year: 2016, Page(s):2778 - 2786
Cited by:  Papers (3)
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Models of coupling noise from an aggressor module to a victim module by way of through silicon vias (TSVs) within heterogeneous 3-D integrated circuits (ICs) are presented in this paper. Existing TSV models are enhanced for different substrate materials within heterogeneous 3-D ICs. Each model is adapted to each substrate material according to the local noise coupling characteristics. The 3-D nois... View full abstract»

• ### Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling

Publication Year: 2016, Page(s):2787 - 2798
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Extensive research has been conducted on a statistical timing analysis of digital integrated circuits in the existence of statistical parameter variations. However, the proposed methods either lack accuracy or efficiency, which avoids coming up with an industry standard tool. Despite this fact, there is a certain consensus that Monte Carlo (MC) methods are accurate, so that they are called golden.... View full abstract»

• ### Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces

Publication Year: 2016, Page(s):2799 - 2802
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Most existing solutions to pipelining nested loops are developed for general purpose processors, and may not work efficiently for field-programmable gate arrays due to loop control overhead. This is especially true when the nested loops have nonrectangular iteration spaces (IS). Thus we propose a novel method that can transform triangular IS-the most frequently found type of nonrectangular IS-into... View full abstract»

• ### An Equalizer With Controllable Transfer Function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort Receivers in 28-nm UTBB-FDSOI

Publication Year: 2016, Page(s):2803 - 2807
Cited by:  Papers (2)
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A multistage continuous-time linear equalizer (CTLE) design with a controllable transfer function is presented. The entire frequency range of interest, from dc to gain roll-off frequency, is divided into six regions, and the transfer function in each region is independently matched to be the inverse of the channel transfer function. The equalizer is used for 6-Gb/s data transfer per channel for hi... View full abstract»

• ### A Flexible-Weighted Nonbinary Searching Technique for High-Speed SAR-ADCs

Publication Year: 2016, Page(s):2808 - 2812
Cited by:  Papers (1)
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This brief presents a low-computational, flexible nonbinary searching technique for high-speed successive approximation register (SAR) analog-to-digital converters (ADCs). By embedding the redundant weights into each capacitor branch of digital-to-analog converter (DAC) array, the conventional binary DAC array is customized as a nonbinary DAC array without additional control logics, resulting in f... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2016, Page(s): C3
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu