IEEE Transactions on Circuits and Systems II: Express Briefs

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Displaying Results 1 - 23 of 23

Publication Year: 2016, Page(s):C1 - C4
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• IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Publication Year: 2016, Page(s): C2
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• A Resistorless Low-Power Voltage Reference

Publication Year: 2016, Page(s):613 - 617
Cited by:  Papers (2)
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A novel low-power temperature-stable voltage reference without resistors is presented in this brief, which is compatible with standard CMOS technology. In order to reduce the temperature nonlinearity in the proposed voltage reference, threshold voltage and a proportional-to-absolute-temperature voltage form the basic linear-temperature components, which are achieved by resistorless threshold volta... View full abstract»

• A Multilevel Class-D CMOS Power Amplifier for an Out-Phasing Transmitter With a Nonisolated Power Combiner

Publication Year: 2016, Page(s):618 - 622
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This brief presents a nonisolated multilevel linear amplifier with nonlinear component (LINC) power amplifier (PA) implemented in a standard 0.18-μm complementary metal-oxide- semiconductor process. Using a nonisolated power combiner, the overall power efficiency is increased by reducing the wasted power at the combined out-phased signal; however, the efficiency at low power still needs to ... View full abstract»

• A 54- $\mu\text{W}$ Inverter-Based Low-Noise Single-Ended to Differential VGA for Second Harmonic Ultrasound Probes in 65-nm CMOS

Publication Year: 2016, Page(s):623 - 627
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This brief presents an inverter-based low-noise single-ended to differential continuous-time variable gain amplifier (VGA) for 2-6-MHz second harmonic cardiac ultrasound imaging probes. The proposed VGA is based on a transimpedance amplifier and composed of resistive arrays and three equal inverters to form the resistive feedback loop. The inverters operate in the class C mode by being biased in t... View full abstract»

• Thermal-Noise-Canceling Switched-Capacitor Circuit

Publication Year: 2016, Page(s):628 - 632
Cited by:  Papers (2)
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Thermal noise has been a fundamental bottleneck in building high dynamic range switched capacitor (SC) circuits. This brief proposes an SC thermal-noise-canceling circuit. The technique, demonstrated using a unity-gain sample-and-hold amplifier (SHA) in IBM 32-nm silicon-on-insulator (SOI) process, gives 5.0-, 4.4-, and 3.7-dB improvements while operating at 100, 250, and 500 MHz, respectively, an... View full abstract»

• A Digital PLL Using Oversampling Delta-Sigma TDC

Publication Year: 2016, Page(s):633 - 637
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A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter (ΔΣTDC) is presented. This ΔΣTDC adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed ΔΣTDC consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm2. The mea... View full abstract»

Publication Year: 2016, Page(s):638 - 642
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This brief presents a novel analog-to-digital converter (ADC) with adaptive delta-sampling for ultra-low power sensing applications. By sampling only the incremental value of the input signal and adaptively adjusting the sampling frequency, the proposed ADC can achieve the same resolution and conversion range with less number of bits than the conventional ADC. Meanwhile, the power consumption is a... View full abstract»

• Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

Publication Year: 2016, Page(s):643 - 647
Cited by:  Papers (3)
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This brief proposes the design of a low-voltage static random access memory (SRAM) for biomedical chip applications. The SRAM is designed using a standard 8T bit cell, featuring a shared data-aware write scheme and a differential reference-based sense amplifier. The proposed techniques make it possible for the 8T SRAM to use bit-interleaving architecture and address the half-select problem, achiev... View full abstract»

• NR-DCSK: A Noise Reduction Differential Chaos Shift Keying System

Publication Year: 2016, Page(s):648 - 652
Cited by:  Papers (16)
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One of the major drawbacks of the conventional differential chaos shift keying (DCSK) system is the addition of channel noise to both the reference signal and the data-bearing signal, which deteriorates its performance. In this brief, we propose a noise reduction DCSK system as a solution to reduce the noise variance present in the received signal in order to improve performance. For each transmit... View full abstract»

• On Impedance Matching in a Power-Line-Communication System

Publication Year: 2016, Page(s):653 - 657
Cited by:  Papers (3)
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Impedance matching plays an important role in a power-line-communication system. We investigate the effect on the signal-to-noise ratio at the receiver and on the system capacity of three different impedance matching criteria at the transmitter, assuming broad-band communication. We show that optimal impedance matching shall maximize the amplitude of the signal voltage at the channel input port. S... View full abstract»

• Transformer-Based Tunable Matching Network Design Techniques in 40-nm CMOS

Publication Year: 2016, Page(s):658 - 662
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A fully integrated transformer-based tunable impedance-matching network is described. The tuning network independently tunes the real and imaginary parts of the impedance. A test chip implemented in a 40-nm CMOS process achieves the resistive tuning range of one octave, making it suitable for shared Bluetooth/Wi-Fi power amplifier (PA) applications. The main sources of insertion loss are identifie... View full abstract»

• Periodic Behaviors for Discrete-Time Second-Order Multiagent Systems With Input Saturation Constraints

Publication Year: 2016, Page(s):663 - 667
Cited by:  Papers (2)
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This brief considers the existence of periodic behaviors for discrete-time second-order multiagent systems with input saturation constraints. We first consider the case where the agent dynamics is a double integrator and then establish conditions on the feedback gains of the linear consensus control law for achieving periodic behaviors. This, in turn, shows that the previously established sufficie... View full abstract»

• A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation

Publication Year: 2016, Page(s):668 - 672
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Affine computation is an important part in many vision applications. It is characterized by intensive computation and dependence of cascade memory access. This brief first implements operation fusion based on the data patterns to break the cascade dependence of memory access, and perform memory partitioning for memory-centric optimization to enhance data throughput and data reuse. Then, based on t... View full abstract»

• Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes

Publication Year: 2016, Page(s):673 - 677
Cited by:  Papers (3)
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This brief presents an efficient sorting architecture for successive-cancellation-list decoding of polar codes. In order to avoid performing redundant sorting operations on the metrics that are already sorted in the previous step of decoding, the proposed architecture separately processes the sorted metrics and unsorted ones. In addition, the odd-even sort network is adopted as a basic building bl... View full abstract»

• Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design

Publication Year: 2016, Page(s):678 - 682
Cited by:  Papers (9)
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Spin-transfer torque (STT) random access memory has been researched as a promising alternative for static random access memory in reconfigurable fabrics, particularly in lookup tables (LUTs), due to its nonvolatility, low standby and static power, and high integration density features. In this brief, we leverage physical characteristics of magnetic tunnel junctions (MTJs) to design a unique refere... View full abstract»

• A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation

Publication Year: 2016, Page(s):683 - 687
Cited by:  Papers (13)
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The digital low dropout regulator (D-LDO) has drawn significant attention recently for its low-voltage operation and process scalability. However, the tradeoff between current efficiency and transient response speed has limited its applications. In this brief, a coarse-fine-tuning technique with burst-mode operation is proposed to the D-LDO. Once the voltage undershoot/ overshoot is detected, the ... View full abstract»

• Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance

Publication Year: 2016, Page(s):688 - 692
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A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations... View full abstract»

• Cooperation of Multiagent Systems With Mismatch Parameters: A Viewpoint of Power Systems

Publication Year: 2016, Page(s):693 - 697
Cited by:  Papers (1)
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This brief addresses a weak cooperation behavior, i.e., position cohesion and velocity consensus for a class of second-order multiagent systems with mismatch parameters from a viewpoint of power systems. All the agents can possess mismatch parameters and receive only the position information from its neighbors throughout the communication network. Sufficient conditions are established, and the hid... View full abstract»

• Influence of Amplitude Fluctuations on the Noise-Induced Frequency Shift of Noisy Oscillators

Publication Year: 2016, Page(s):698 - 702
Cited by:  Papers (4)
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We discuss the effect of the estimation of the amplitude variations on the noise-induced frequency shift in nonlinear oscillators. The analysis is based on a general reduction approach to a phase macromodel making use of the Itô interpretation of the stochastic differential equations representing noisy autonomous systems. We show that a significant improvement of the accuracy can be obtain... View full abstract»

• Efficient WLS Design of IIR Digital Filters Using Partial Second-Order Factorization

Publication Year: 2016, Page(s):703 - 707
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In this brief, a novel algorithm is developed for the design of infinite-impulse-response digital filters in the weighted least-squares sense. To simplify the design problem, the Levy linearized function and the Sanathanan-Koerner iterative technique are utilized. In the proposed algorithm, a denominator polynomial is decomposed as a cascade of a few second-order factors (SOFs) and a higher order ... View full abstract»

• A Low-Latency QRD-RLS Architecture for High-Throughput Adaptive Applications

Publication Year: 2016, Page(s):708 - 712
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A novel architecture for QR decomposition-based recursive least squares is presented. It offers low latency for applications where the channel equalization and adaptive filtering are mandatory. This approach reduces the computations by rewriting the equations in a manner that lets intense hardware resource sharing by reusing similar values in different computations. Moreover, precision range conve... View full abstract»

• IEEE Circuits and Systems Society Information

Publication Year: 2016, Page(s): C3
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Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org