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IEEE Computer Architecture Letters

Issue 1 • Jan.-June 2016

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Displaying Results 1 - 24 of 24
  • Table of Contents

    Publication Year: 2016, Page(s): C1
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  • Cover

    Publication Year: 2016, Page(s): C2
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  • A Methodology for Cognitive NoC Design

    Publication Year: 2016, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (225 KB) | HTML iconHTML

    The number of cores in a multicore chip design has been increasing in the past two decades. The rate of increase will continue for the foreseeable future. With a large number of cores, the on-chip communication has become a very important design consideration. The increasing number of cores will push the communication complexity level to a point where managing such highly complex systems requires ... View full abstract»

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  • Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip

    Publication Year: 2016, Page(s):5 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB) | HTML iconHTML

    3D logic-on-logic technology is a promising approach for extending the validity of Moore's law when technology scaling stops. 3D technology can also lead to a paradigm shift in on-chip communication design by providing orders of magnitude higher bandwidth and lower latency for inter-layer communication. To turn the 3D technology bandwidth and latency benefits into network latency reductions and pe... View full abstract»

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  • End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance

    Publication Year: 2016, Page(s):9 - 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (518 KB) | HTML iconHTML

    Interconnection networks are a critical component in most modern systems nowadays. Both off-chip networks, in HPC systems, data centers, and cloud servers, and on-chip networks, in chip multiprocessors (CMPs) and multiprocessors system-on-chip (MPSoCs), play an increasing role as their performance is vital for the performance of the whole system. One of the key components of any interconnect is th... View full abstract»

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  • Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers

    Publication Year: 2016, Page(s):13 - 16
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (939 KB) | HTML iconHTML

    Hardware prefetching improves system performance by hiding and tolerating the latencies of lower levels of cache and off-chip DRAM. An accurate prefetcher improves system performance whereas an inaccurate prefetcher can cause cache pollution and consume additional bandwidth. Prefetch address filtering techniques improve prefetch accuracy by predicting the usefulness of a prefetch address and based... View full abstract»

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  • Exploiting Existing Copies in Register File for Soft Error Correction

    Publication Year: 2016, Page(s):17 - 20
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB) | HTML iconHTML

    Soft errors are an increasingly important problem in contemporary digital systems. Being the major data holding component in contemporary microprocessors, the register file has been an important part of the processor on which researchers offered many different schemes to protect against soft errors. In this paper we build on the previously proposed schemes and start with the observation that many ... View full abstract»

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  • Hardware Enforced Statistical Privacy

    Publication Year: 2016, Page(s):21 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    The Internet of Things will result in users generating vast quantities of data, some of it sensitive. Results from the statistical analysis of sensitive data across wide ranges of demographics will become ever more useful to data analysts and their clients. The competing needs of the two groups-data generators with their desire for privacy and analysts with their desire for inferred statistics-wil... View full abstract»

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  • Inter-Core Locality Aware Memory Scheduling

    Publication Year: 2016, Page(s):25 - 28
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (658 KB) | HTML iconHTML

    Graphics Processing Units (GPUs) run thousands of parallel threads and achieve high Memory Level Parallelism (MLP). To support high Memory Level Parallelism, a structure called a Miss-Status Holding Register (MSHR) handles multiple in-flight miss requests. When multiple cores send requests to the same cache line, the requests are merged into one last level cache MSHR entry and only one memory requ... View full abstract»

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  • Non-Intrusive Persistence with a Backend NVM Controller

    Publication Year: 2016, Page(s):29 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (150 KB) | HTML iconHTML

    By providing instruction-grained access to vast amounts of persistent data with ordinary loads and stores, byte-addressable storage class memory (SCM) has the potential to revolutionize system architecture. We describe a non-intrusive SCM controller for achieving light-weight failure atomicity through back-end operations. Our solution avoids costly software intervention by decoupling isolation and... View full abstract»

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  • On-Chip Message Passing Sub-System for Embedded Inter-Domain Communication

    Publication Year: 2016, Page(s):33 - 36
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (442 KB) | HTML iconHTML

    This letter describes the architecture of an inter-domain message passing hardware sub-system targeting the embedded virtualization field. Embedded virtualization is characterized by application-specific solutions, where functionality is partitioned into a small, fixed number of Virtual Machines, typically under real-time constraints, which must communicate for synchronization and status signaling... View full abstract»

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  • PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor

    Publication Year: 2016, Page(s):37 - 40
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB) | HTML iconHTML

    Hardware prefetching on IBM's latest POWER8 processor is able to improve performance of many applications significantly, but it can also cause performance loss for others. The IBM POWER8 processor provides one of the most sophisticated hardware prefetching designs which supports 225 different configurations. Obviously, it is a big challenge to find the optimal or near-optimal hardware prefetching ... View full abstract»

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  • pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems

    Publication Year: 2016, Page(s):41 - 44
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB) | HTML iconHTML

    Improving the performance and power efficiency of a single processor has been fraught with various challenges stemming from the end of the classical technology scaling. Thus, the importance of efficiently running applications on a parallel/distributed computer system has continued to increase. In developing and optimizing such a parallel/distributed computer system, it is critical to study the imp... View full abstract»

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  • Ramulator: A Fast and Extensible DRAM Simulator

    Publication Year: 2016, Page(s):45 - 49
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (523 KB) | HTML iconHTML

    Recently, both industry and academia have proposed many different roadmaps for the future of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which can be easily modified to judge the merits of today's DRAM standards as well as those of tomorrow. In this paper, we present Ramulator, a fast and cycle-accurate DRAM simulator that is built from the ground up for extensibi... View full abstract»

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  • Security Implications of Third-Party Accelerators

    Publication Year: 2016, Page(s):50 - 53
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (83 KB) | HTML iconHTML

    Third-party accelerators offer system designers high performance and low energy without the market delay of in-house development. However, complex third-party accelerators may include vulnerabilities due to design flaws or malicious intent that are hard to expose during verification. Rather than react to each new vulnerability, it is better to proactively build defenses for classes of attacks. To ... View full abstract»

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  • The Case for VLIW-CMP as a Building Block for Exascale

    Publication Year: 2016, Page(s):54 - 57
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (547 KB) | HTML iconHTML

    Current ultra-high-performance computers execute instructions at the rate of roughly 10 PFLOPS (10 quadrillion floating-point operations per second) and dissipate power in the range of 10 MW. The next generation will need to execute instructions at EFLOPS rates-100X as fast as today's-but without dissipating any more power. To achieve this challenging goal, the emphasis is on power-efficient execu... View full abstract»

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  • Toward Multi-Layer Holistic Evaluation of System Designs

    Publication Year: 2016, Page(s):58 - 61
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (291 KB) | HTML iconHTML

    The common practice for quantifying the benefit(s) of design-time architectural choices of server processors is often limited to the chip- or server-level. This quantification process invariably entails the use of salient metrics, such as performance, power, and reliability, which capture-in a tangible manner-a designs overall ramifications. This paper argues for the necessity of a more holistic e... View full abstract»

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  • Towards High-Performance Bufferless NoCs with SCEPTER

    Publication Year: 2016, Page(s):62 - 65
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB) | HTML iconHTML

    In the many-core era, the network on-chip (NoC) is playing a larger role in meeting performance, area and power goals, as router buffers contribute greatly to NoC area and power usage. Proposals have advocated bufferless NoCs, however a performance wall has been reached such that high throughput performance has not been extracted. We present SCEPTER, a high-performance bufferless mesh NoC that set... View full abstract»

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  • Introducing IEEE Collabratec

    Publication Year: 2016, Page(s): 66
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  • Experience the Newest and Most Advanced Thinking in Big Data Analytics

    Publication Year: 2016, Page(s): 67
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  • IEEE Cyber Security

    Publication Year: 2016, Page(s): 68
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  • 2015 Index IEEE Computer Architecture Letters Vol. 14

    Publication Year: 2016, Page(s):1 - 6
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  • Cover

    Publication Year: 2016, Page(s): C3
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  • Back Cover [Table of contents, continued]

    Publication Year: 2016, Page(s): C4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Daniel J. Sorin
Duke University
Electrical & Computer Engineering
PO Box 90291
Durham, NC 27708
e-mail: sorin@ee.duke.edu