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# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 23 of 23

Publication Year: 2016, Page(s):C1 - C4
| PDF (43 KB)
• ### IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Publication Year: 2016, Page(s): C2
| PDF (39 KB)
• ### A Simplified Model for Passive-Switched-Capacitor Filters With Complex Poles

Publication Year: 2016, Page(s):513 - 517
Cited by:  Papers (1)
| | PDF (806 KB) | HTML

This brief demonstrates a method to realize complex conjugate poles using passive-switched-capacitor networks. In addition, a simplified continuous-time model will be introduced so that accurate transfer functions and output noise can be obtained without the need for complicated charge-balance equations and thereby allow a better intuitive understanding of these structures. The developed theory is... View full abstract»

• ### A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs

Publication Year: 2016, Page(s):518 - 522
| | PDF (1421 KB) | HTML

A background timing-mismatch calibration algorithm is proposed, which detects and corrects the sampling time mismatches in time-interleaved analog-to-digital converter (ADC) channels by analyzing the sign-equality of a reference slope and a timing-mismatch-induced error value. The sign of the ideal derivative along the input is estimated through the adjacent channel outputs, thus not requiring an ... View full abstract»

• ### A 0.5-V 1.3- $\mu\text{W}$ Analog Front-End CMOS Circuit

Publication Year: 2016, Page(s):523 - 527
Cited by:  Papers (6)
| | PDF (1298 KB) | HTML

This brief presents a low-power analog acquisition front-end circuit for a Wireless Body Area Network. This front-end system mainly consists of three parts, namely, chopped capacitively coupled instrumentation amplifier (CCIA), switched capacitor filter (SC-filter), and successive-approximation analog-to-digital converter. In order to reduce the power consumption, the supply voltage is scaled to 0... View full abstract»

• ### A 64-Channel 965- $mutext{W}$ Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS

Publication Year: 2016, Page(s):528 - 532
Cited by:  Papers (3)
| | PDF (858 KB) | HTML

This brief presents a 64-channel neural recording system-on-chip (SoC) with a 20-Mb/s wireless telemetry. Each channel of the analog front end consists of a low-noise bandpass amplifier, featuring a noise efficiency factor of 3.11 with an input-referred noise of 5.6 μVrms in a 0.001- to 10-kHz band and a 31.25-kSps 6-fJ/conversion-step 10-bit SAR analog-to-digital converter. The ... View full abstract»

• ### A Two-Stage Broadband Fully Integrated CMOS Linear Power Amplifier for LTE Applications

Publication Year: 2016, Page(s):533 - 537
Cited by:  Papers (3)
| | PDF (1289 KB) | HTML

This brief presents the implementation and measurement results of a CMOS broadband linear power amplifier (PA) for long-term evolution (LTE) applications. Interstage matching considering the main's source and the driver's load impedances is analyzed for broadband linear output power. The proposed PA is fabricated in standard 0.11-μm RF CMOS technology. The PA achieves linear output power of... View full abstract»

• ### Still More on the $1/f^{2}$ Phase Noise Performance of Harmonic Oscillators

Publication Year: 2016, Page(s):538 - 542
Cited by:  Papers (2)
| | PDF (389 KB) | HTML

Modeling tank losses in a harmonic oscillator by means of an equivalent parallel resistance may lead to an optimistic estimate of phase noise, as recently experienced in a class-D CMOS oscillator. The discrepancy is significant if two conditions are fulfilled: The single-ended portion of the tank capacitance displays a non-negligible loss, and the loop gain of the oscillator is very large; in the ... View full abstract»

• ### Quadruply Split Cross-Driven Doubly Recycled $g_{{m}}$-Doubling Recycled Folded Cascode for Microsensor Instrumentation Amplifiers

Publication Year: 2016, Page(s):543 - 547
Cited by:  Papers (1)
| | PDF (1523 KB) | HTML

The requirement of high gain and low noise for sensor readout instrumentation is addressed in this brief. A novel current cross-mirroring technique is employed to enhance the small signal current of the proposed quadruply split cross-driven doubly recycled folded cascode (RFC) operational transconductance amplifier. The small signal current is increased by using split devices and two mirroring rat... View full abstract»

• ### A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO

Publication Year: 2016, Page(s):548 - 552
Cited by:  Papers (2)
| | PDF (1312 KB) | HTML

A low-voltage phase-locked-loop (PLL) circuit with a supply-noise-compensated feedforward ring voltage-controlled oscillator (FRVCO) is demonstrated. The oscillation frequency fluctuation due to supply noise is compensated by adjusting the ratio of driving strength in feedforward and direct paths in FRVCO. A prototype 400-MHz PLL circuit operating at 0.65 V is fabricated with 180-nm standard CMOS ... View full abstract»

• ### A Sub-1.0-V On-Chip CMOS Thermometer With a Folded Temperature Sensor for Low-Power Mobile DRAM

Publication Year: 2016, Page(s):553 - 557
| | PDF (1606 KB) | HTML

As Dynamic Random Access Memory (DRAM) supply voltages drop below 1 V with the scaling down of the process, it becomes increasingly difficult to construct a temperature sensor with sufficient accuracy to control self-refresh, without occupying significant area or consuming increased power. In this brief, we propose an on-chip CMOS thermometer with a temperature sensor, the output of which is divid... View full abstract»

• ### A Memristive Pascaline

Publication Year: 2016, Page(s):558 - 562
Cited by:  Papers (4)
| | PDF (6639 KB) | HTML

The original Pascaline was a mechanical calculator able to sum and subtract integers. It encodes information in the angles of the mechanical components (such as wheels and cylinders), is aided by gravity, and performs the calculations. Here, we show that such a concept can be realized in electronics using memory elements such as memristive systems. By using memristive emulators, we have demonstrat... View full abstract»

• ### Finite-Time Consensus Tracking of Perturbed High-Order Agents With Relative Information by Integral Sliding Mode

Publication Year: 2016, Page(s):563 - 567
Cited by:  Papers (4)
| | PDF (466 KB) | HTML

Finite-time consensus tracking of high-order multiagent systems (MASs) with disturbances is investigated with relative information only. First, the MASs are converted to the dynamics of local consensus errors with relative states only, and the high-order finite-time exact differentiators are employed to estimate the unknown consensus errors when only the relative outputs of the MAS are available. ... View full abstract»

• ### An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication

Publication Year: 2016, Page(s):568 - 572
Cited by:  Papers (1)
| | PDF (1225 KB) | HTML

To achieve low latency, existing radix-4 scalable architectures for word-based Montgomery modular multiplication usually suffer from high design and hardware complexities. This brief presents a simple compression scheme and circuit to remove the data dependence in the accumulation process and accomplish one-cycle latency without quotient pipeline. The complex computation and encoding of quotient d... View full abstract»

• ### A Low-Power Two-Tap Voltage-Mode Transmitter With Precisely Matched Output Impedance Using an Embedded Calibration Circuit

Publication Year: 2016, Page(s):573 - 577
Cited by:  Papers (2)
| | PDF (1136 KB) | HTML

In this brief, a low-power two-tap voltage-mode transmitter (TX) with precisely matched output impedance using an embedded calibration circuit for dc-coupled unidirectional links is proposed. The proposed TX adopts an N-over-N driver with a supply voltage of 0.4 V in order to reduce the power consumption of the output driver. Its output driver is configured as a two-tap Finite Impulse Response (FI... View full abstract»

• ### Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM

Publication Year: 2016, Page(s):578 - 582
| | PDF (878 KB) | HTML

Spin-transfer-torque random access memory (STT-RAM) has attracted much research interest for its characteristics of scalability, nonvolatility, and small cell size. As the technology node is scaled down, however, the sensing margin (SM) and read disturbance margin (RDM) of the STT-RAM are degraded because of increased process variation, decreased supply voltage, and reduced critical switching curr... View full abstract»

• ### OFDM Multitone Signal Generation Technique for Analog Circuitry Test Characterization

Publication Year: 2016, Page(s):583 - 587
Cited by:  Papers (1)
| | PDF (879 KB) | HTML

Multitone test is an effective technique in many wideband circuit test applications. However, the traditional multitone test signal generation methods are complex and/or time consuming. In this brief, a new approach utilizing orthogonal frequency-division multiplexing technique is developed, which can effectively produce multiple frequency tones concurrently with fine resolution and low design ove... View full abstract»

• ### Improved-Variable-Forgetting-Factor Recursive Algorithm Based on the Logarithmic Cost for Volterra System Identification

Publication Year: 2016, Page(s):588 - 592
Cited by:  Papers (14)
| | PDF (805 KB) | HTML

Compared with the least-mean-square algorithm, the least mean pth power algorithm shows a better robustness performance against impulsive noises such as the α-stable noises. However, it still exhibits slow convergence rate and high kernel misadjustment. To overcome this drawback, a novel recursive logarithmic least mean pth (RLLMP) algorithm is proposed for the Volterra system identificatio... View full abstract»

• ### Quantization Noise Power Estimation for Floating-Point DSP Circuits

Publication Year: 2016, Page(s):593 - 597
Cited by:  Papers (1)
| | PDF (875 KB) | HTML

In this brief, we present a semianalytical model of the quantization noise power of floating-point DSP circuits, considering heterogeneous precisions. The use of hardware operators with optimized precisions has proven to provide important cost reductions. However, precision optimization is a time-consuming task, and fast and accurate error estimators are required. Moreover, the use of the signal-t... View full abstract»

• ### Monolithic Low-Power 6-Gb/s Optical Transmitter for a Silicon HBT-Based Carrier Injection Electroabsorption Modulator

Publication Year: 2016, Page(s):598 - 602
| | PDF (1366 KB) | HTML

Photonic devices monolithically integrated with nanoscale electronic signal processing circuitry in silicon are emerging as a disruptive technology to reduce cost and improve optical system integration and performance. Silicon heterojunction bipolar transistor (HBT)-based carrier injection electroabsorption modulators (EAMs) implemented in a commercial silicon process have several merits, includin... View full abstract»

• ### A Novel Hardware-Efficient Asynchronous Cellular Automaton Model of Spike-Timing-Dependent Synaptic Plasticity

Publication Year: 2016, Page(s):603 - 607
Cited by:  Papers (3)
| | PDF (1496 KB) | HTML

The spike-timing-dependent synaptic plasticity (STDP) is a form of change of a synaptic weight depending on timings of pre- and post synaptic spikes. In this brief, a novel asynchronous cellular automaton model of the STDP is presented. It is shown that the presented model can reproduce various STDP characteristics observed in physiological experiments. Also, the presented model is implemented in ... View full abstract»

• ### A Low-Cost Low-Power Ring Oscillator-Based Truly Random Number Generator for Encryption on Smart Cards

Publication Year: 2016, Page(s):608 - 612
Cited by:  Papers (6)
| | PDF (1574 KB) | HTML

The design of a low-cost low-power ring oscillator-based truly random number generator (TRNG) macrocell, which is suitable to be integrated in smart cards, is presented. The oscillator sampling technique is exploited, and a tetrahedral oscillator with large jitter has been employed to realize the TRNG. Techniques to improve the statistical quality of the ring oscillatorbased TRNGs' bit sequences h... View full abstract»

• ### IEEE Circuits and Systems Society Information

Publication Year: 2016, Page(s): C3
| PDF (33 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org