# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 69

Publication Year: 2016, Page(s):C1 - 2230
| |PDF (160 KB)
• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2016, Page(s): C2
| |PDF (138 KB)
• ### Review on Thermionic Energy Converters

Publication Year: 2016, Page(s):2231 - 2241
Cited by:  Papers (7)
| |PDF (1888 KB) | HTML

Thermionic energy converter (TEC) is a heat engine that generates electricity directly using heat as its source of energy and electron as its working fluid. Despite having a huge potential as an efficient direct energy conversion device, the progress in vacuum-based thermionic energy converter development has always been hindered by the space charge problem and the unavailability of materials with... View full abstract»

• ### Silicon Carbide Fully Differential Amplifier Characterized Up to 500 °C

Publication Year: 2016, Page(s):2242 - 2247
Cited by:  Papers (5)
| |PDF (3543 KB) | HTML

This paper presents a monolithic fully differential amplifier implemented in a low-voltage 4H-silicon carbide bipolar junction transistor technology. The circuit has been designed, considering the variation of device parameters over a large temperature range. A base-current compensation technique has been applied to overcome the low input resistance of the amplifier. The bare chip of the amplifier... View full abstract»

• ### Physically Based Predictive Model for Single Event Transients in CMOS Gates

Publication Year: 2016, Page(s):2248 - 2254
Cited by:  Papers (2)
| |PDF (1223 KB) | HTML

An analytical model is presented to understand the time response of an inverter to ionizing particles based on physical equations. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain-body junction of the OFF-state nMOS is represented as a photocurrent pulse. If this current source is large enough, th... View full abstract»

• ### A Comprehensive Analytical Study of Dielectric Modulated Drift Regions—Part I: Static Characteristics

Publication Year: 2016, Page(s):2255 - 2260
Cited by:  Papers (1)
| |PDF (1792 KB) | HTML

A comprehensive study of dielectric modulated (DM) drift regions for power devices is presented in this paper. The performance of this structure is theoretically analyzed and compared with both conventional and superjunction (SJ) structures. In this paper, an analytical model for DM drift regions with cylindrical cells is proposed and compared with linear cells. An optimal tradeoff between breakdo... View full abstract»

• ### A Comprehensive Analytical Study on Dielectric Modulated Drift Regions—Part II: Switching Performances

Publication Year: 2016, Page(s):2261 - 2267
| |PDF (1556 KB) | HTML

A comprehensive study on the dielectric modulated (DM) drift region for power devices is presented in this paper. The performance of this drift region structure is theoretically analyzed and compared with other two structures: conventional and superjunction. In this paper, a study is focused on switching performance. The C-V relationships during switching are analytically derived, and the depletio... View full abstract»

• ### Anomalous TDDB Statistics of Gate Dielectrics Caused by Charging-Induced Dynamic Stress Relaxation Under Constant–Voltage Stress

Publication Year: 2016, Page(s):2268 - 2274
Cited by:  Papers (2)
| |PDF (1209 KB) | HTML

Anomalous Time Dependent Dielectric Breakdown (TDDB) statistics of thick gate dielectrics, i.e., too large stress field/voltage dependence and nonlinear Weibull plot of TDDB lifetime, have been observed. Through the analysis of behaviors under the TDDB stress and also the comparison with thin gate dielectrics, it has been revealed that just the intrinsic charging of injected carriers to initial an... View full abstract»

• ### A Charge-Plasma-Based Transistor With Induced Graded Channel for Enhanced Analog Performance

Publication Year: 2016, Page(s):2275 - 2281
Cited by:  Papers (8)
| |PDF (1852 KB) | HTML

In this paper, using the charge-plasma concept, we propose an effective technique to implement a graded channel (GC) nanoscale MOSFET without the need for a separate implantation. The characteristics are demonstrated and compared with conventional dopingless, junctionless, and underlap inversion-mode MOSFET. The results show that the proposed GC device exhibits reduced drain-induced barrier loweri... View full abstract»

• ### Modeling a Dual-Material-Gate Junctionless FET Under Full and Partial Depletion Conditions Using Finite-Differentiation Method

Publication Year: 2016, Page(s):2282 - 2287
Cited by:  Papers (1)
| |PDF (2193 KB) | HTML

In this paper, we have developed a model for the surface potential and the drain current of a dual-material double-gate (DMDG) junctionless FET (JLFET) transistor. A finite-differentiation method has been used to decompose the 2-D Poisson's equation into two 1-D equations, which allows the modeling of the DMDG structure as two individual single-material double-gate JLFETs. The two 1-D models are t... View full abstract»

• ### Joule Heating to Enhance the Performance of a Gate-All-Around Silicon Nanowire Transistor

Publication Year: 2016, Page(s):2288 - 2292
| |PDF (1829 KB) | HTML

Thermal engineering assisted by electrical annealing was applied to enhance the device performance of a gate-all-around (GAA) silicon nanowire (Si-NW) transistor. The ON-state current is increased by four times. Joule heating was produced in a Si-NW by electrical biasing. The heating was concentrated on both edges of the gate, which served as a heat sink, effectively lowering the parasitic externa... View full abstract»

• ### Tradeoff Between Low-Power Operation and Radiation Hardness of Fully Depleted SOI pMOSFET by Changing LDD Conditions

Publication Year: 2016, Page(s):2293 - 2298
Cited by:  Papers (1)
| |PDF (1554 KB) | HTML

The interrelation between off-leakage as consideration of low-power operation and X-ray radiation hardness has been evaluated in view of optimizing the lightly doped drain (LDD) concentration of fully depleted silicon-on-insulator pMOSFET. The MOSFET with relatively low LDD concentration called ultralow-power P channel LDD (ULP-PLDD) shows a lower off-leakage of 0.1 pA/μm but limited X-ray ... View full abstract»

• ### Analytical Modeling of Channel Potential and Threshold Voltage of Double-Gate Junctionless FETs With a Vertical Gaussian-Like Doping Profile

Publication Year: 2016, Page(s):2299 - 2305
Cited by:  Papers (7)
| |PDF (1284 KB) | HTML

This paper proposes an analytical 2-D model for the channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile. The 2-D Poisson equation has been solved by using the evanescent-mode analysis to obtain the potential distribution function in the channel. The position of the conduction path also has been modeled to calculate the potential at ... View full abstract»

• ### An Improved Surface Roughness Scattering Model for Bulk, Thin-Body, and Quantum-Well MOSFETs

Publication Year: 2016, Page(s):2306 - 2312
Cited by:  Papers (6)
| |PDF (1031 KB) | HTML

This paper reports about the implementation in a multisubband Monte Carlo device simulator of a comprehensive surface roughness scattering model, based on a nonlinear relation between the scattering matrix elements and the fluctuations Δ(r) of the interface position. The model is first extended by including carrier screening effects and accounting for scattering at multiple interfaces, and ... View full abstract»

• ### Impact of a Spacer Layer on the Analog Performance of Asymmetric InP/InGaAs nMOSFETs

Publication Year: 2016, Page(s):2313 - 2320
Cited by:  Papers (6)
| |PDF (2671 KB) | HTML

An extensive numerical analysis is performed to study and evaluate the impact of a dielectric sidewall spacer layer on the various device parameters associated with analog circuit performance of In0.75Ga0.25As channel asymmetric nMOSFETs with InP drain at two different channel lengths (Lg) of 20 and 30 nm. The numerical simulation deck is calibrated with asymmetric... View full abstract»

• ### Experimental Benchmarking of Electrical Methods and $mu$ -Raman Spectroscopy for Channel Temperature Detection in AlGaN/GaN HEMTs

Publication Year: 2016, Page(s):2321 - 2327
Cited by:  Papers (2)
| |PDF (1784 KB) | HTML

In this paper, several experimental methods (electrical and optical) for channel temperature detection in AlGaN/GaN high-electron mobility transistors have been studied and experimentally benchmarked. This paper encompasses four electrical methods (two dc characterization methods, low-RF output conductance measurement, and gate-resistive sensing technique) and one optical method (micro-Raman spect... View full abstract»

• ### An Optically Readable InGaN/GaN RRAM

Publication Year: 2016, Page(s):2328 - 2333
| |PDF (1022 KB) | HTML

The unidirectional bipolar resistance switching in GaN/InGaN-based light-emitting diode (LED) was discovered to explore optically readable resistive random access memory (RRAM) device. The device displays stable resistance window in both endurance and retention tests, showing good nonvolatility for memory application. The light-emitting state of this device can also be tuned by the resistance swit... View full abstract»

• ### Time-Dependent Failure of GaN-on-Si Power HEMTs With p-GaN Gate

Publication Year: 2016, Page(s):2334 - 2339
Cited by:  Papers (17)
| |PDF (1771 KB) | HTML

This paper reports an experimental demonstration of the time-dependent failure of GaN-on-Si power high-electron-mobility transistors with p-GaN gate, submitted to a forward gate stress. By means of combined dc, optical analysis, and 2-D simulations, we demonstrate the following original results: 1) when submitted to a positive voltage stress (in the range of 7-9 V), the transistors show a time-dep... View full abstract»

• ### Beyond Thermal Management: Incorporating p-Diamond Back-Barriers and Cap Layers Into AlGaN/GaN HEMTs

Publication Year: 2016, Page(s):2340 - 2345
Cited by:  Papers (4)
| |PDF (1712 KB) | HTML

This work explores the use of p-diamond back-barriers (BBs) and cap layers to enhance the performance of GaN-based high electron mobility transistors (HEMTs). Diamond can offer a heavily doped p-type layer, which is complementary to GaN electronics. Self-consistent electrothermal simulations reveal that the use of p-diamond BBs and cap layers can increase the breakdown voltage of GaN-based HEMTs b... View full abstract»

• ### Modeling of Forward Gate Leakage Current in MOSHEMT Using Trap-Assisted Tunneling and Poole–Frenkel Emission

Publication Year: 2016, Page(s):2346 - 2352
Cited by:  Papers (5)
| |PDF (1158 KB) | HTML

Investigation of various forward gate leakage current mechanisms in an AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistor is done in this paper. During high temperature (T>388 K), the trap-assisted tunneling (TAT) mechanism dominates the gate leakage current at low electric field for a range of gate biases from 0 to 0.2 V, whereas the Poole-Frenkel emission is the major compo... View full abstract»

• ### Amplifier Design Using Vertical InAs Nanowire MOSFETs

Publication Year: 2016, Page(s):2353 - 2359
| |PDF (4822 KB) | HTML

In this paper, an amplifier design using ballistic vertical InAs nanowire (NW) transistors is investigated, focusing on a basic common-source amplifier. The maximum power gain at 90 GHz is evaluated for different NW transistor architectures together with the power dissipation. The linearity of the amplifier is evaluated by estimating the IIP3 and 1-dB compression points. Furthermore, th... View full abstract»

• ### Investigation of the Program Operation of NAND Flash Cells With a Single-Electron Resolution

Publication Year: 2016, Page(s):2360 - 2366
Cited by:  Papers (1)
| |PDF (8764 KB) | HTML

This paper exploits the possibility of monitoring the floating-gate (FG) charge of state-of-the-art NAND Flash arrays with a single-electron resolution to investigate in detail the program operation and some previously inaccessible technological parameters. In particular, the analysis leads to the assessment of the statistical distribution of the FG to control-gate capacitance and of the leakage c... View full abstract»

• ### SET/RESET Cycling-Induced Trap Creation and SET-Disturb Failure Time Degradation in a Resistive-Switching Memory

Publication Year: 2016, Page(s):2367 - 2373
Cited by:  Papers (2)
| |PDF (2989 KB) | HTML

Characterization and modeling of SET/RESET cycling-induced SET-disturb failure time degradation in a tungsten oxide resistive random access memory are performed. We find that write-disturb failure time in a high-resistance state (HRS) cell abruptly degrades by the orders of magnitude after certain SET/RESET cycles. To investigate this new degradation mode, we perform the constant voltage stress in... View full abstract»

• ### Ferroelectric/Semiconductor/Tunnel-Junction Stacks for Nondestructive and Low-Power Read-Out Memory

Publication Year: 2016, Page(s):2374 - 2379
| |PDF (758 KB) | HTML

We demonstrate that a tunnel junction connected in series to the ferroelectric (FE) via a semiconductor (SC) layer can be used to 1 probe the polarization state in an FE thin-film capacitor. A thermodynamic analysis is carried out to demonstrate the carrier depletion and accumulation at the SC/tunnel-junction interface as a function of the polarization direction in the FE layer. Our results indica... View full abstract»

• ### Asymmetric Current Behavior on Unipolar Resistive Switching in Pt/HfO2/Pt Resistor With Symmetric Electrodes

Publication Year: 2016, Page(s):2380 - 2383
Cited by:  Papers (1)
| |PDF (715 KB) | HTML

The influence of electrodes on unipolar switching characteristics of a Pt/HfO2/Pt resistor with symmetric electrodes is investigated by comparing the reset voltage (VR), set voltage (VS), current at low resistance state (ILRS) and high resistance state (IHRS), and ILRS/IHRS with positive and negative voltage polarities. T... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy