IEEE Transactions on Circuits and Systems II: Express Briefs

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Publication Year: 2016, Page(s):C1 - C4
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• IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Publication Year: 2016, Page(s): C2
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• Digital Calibration of Amplifier Finite DC Gain and Gain Bandwidth in MASH $SigmaDelta$ Modulators

Publication Year: 2016, Page(s):321 - 325
Cited by:  Papers (1)
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In this brief, a digital background calibration technique is proposed to improve the resolution of discrete-time multistage noise-shaping (MASH) sigma-delta (ΣΔ) modulators. The circuit imperfections of switched-capacitor discrete-time integrators (DTIs) degenerate the modulator output resolution, particularly in MASH structures, due to the quantization noise leakage of the early sta... View full abstract»

• Rank Determination by Winner-Take-All Circuit for Rank Modulation Memory

Publication Year: 2016, Page(s):326 - 330
Cited by:  Papers (1)
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Multilevel-cell (MLC) memory technologies have achieved a great improvement in increasing demand for a high-density memory. As the memory cells utilize a higher number of bits per cell, they have been faced with some problems, such as accurate charge placement and measurement, which slow down programming processes. To overcome these problems, the new data representation technology, rank modulation... View full abstract»

• A Metastability Error Detection and Reduction Technique for Partially Active Flash ADCs

Publication Year: 2016, Page(s):331 - 335
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A metastability error detection and reduction technique for partially active analog-to-digital converters (ADCs) is presented. It detects the metastability condition by comparing the coarse ADC output with a predefined voltage level. The metastability of the proposed comparator-based and prior logic gate-based metastability detectors (MDs) is analyzed. The metastable probability of the MD is shown... View full abstract»

• A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security

Publication Year: 2016, Page(s):336 - 340
Cited by:  Papers (3)
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A 64-kB logic resistive random access memory (RRAM) chip for physically secure key storage is presented. The chip has security features of resisting fully invasive attacks such as deprocessing and microscopy observation, resisting side-channel attacks by providing symmetrical power and timing read signals, resisting malicious writing by a reduced write protection scheme with feedback, and resistin... View full abstract»

• An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency

Publication Year: 2016, Page(s):341 - 345
Cited by:  Papers (2)
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A new pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) structure without residue amplifier and timing-interleaving is presented in this brief. Two redistribution digital-to-analog converters (DACs) and comparators are adopted in two stages, with DAC1 for most significant bit (MSB) comparisons and DAC2 for least significant bit (LSB) compariso... View full abstract»

• Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error

Publication Year: 2016, Page(s):346 - 350
Cited by:  Papers (1)
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A new subthreshold level shifter capable of converting an input signal from a deep subthreshold voltage to an above-threshold voltage is presented in this brief. The circuit utilizes a self-controlled current limiter to implement level shifting by detecting output error. Owing to to this technique, measured results from a 65-nm test chip demonstrate that it can realize a robust voltage conversion ... View full abstract»

• A 2- $\mu\text{W}$ 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop

Publication Year: 2016, Page(s):351 - 355
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This brief presents an ultra-low-power low-noise chopped capacitively coupled instrumentation amplifier (CCIA) that is suitable for neural recording applications. An active high-pass filter is embedded in the ripple reduction loop (RRL) to suppress the residual noise and relax the capacitor size. Multiple chopping is employed to further reduce the residual output ripple due to the RRL offsets. A d... View full abstract»

• A High-Gain 1.75-GHz Dual-Inductor Transimpedance Amplifier With Gate Noise Suppression for Fast Radiation Detection

Publication Year: 2016, Page(s):356 - 360
Cited by:  Papers (1)
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High-speed pulse-shape analysis can allow one to extract the physical parameters that govern radiation interaction. This brief presents a transimpedance preamplifier that can replace conventional configurations that contain a charge-sensitive preamplifier and shaping amplifier chain, particularly for high-speed radiation measurement systems. A transimpedance amplifier is a primary circuit of the p... View full abstract»

• A Switched-Capacitor Filter With Reduced Sensitivity to Reference Noise for Audio-Band Sigma–Delta D/A Converters

Publication Year: 2016, Page(s):361 - 365
Cited by:  Papers (1)
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A switched-capacitor analog reconstruction filter with a new reference switching scheme is presented for reducing sensitivity to reference noise in audio-band sigma-delta (ΣΔ) digital-to-analog converters. By sampling a single reference voltage with its polarity depending on the filter digital input, the ac component of the reference voltage is attenuated by a first-order difference ... View full abstract»

• Sample-and-Hold Asynchronous Sigma-Delta Time Encoding Machine

Publication Year: 2016, Page(s):366 - 370
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In this brief, a new modulation scheme called sample-and-hold asynchronous sigma-delta modulation (SH-ASDM), the extension of the classical asynchronous sigma-delta scheme (ASDM), is introduced. The SH-ASDM is aimed to provide an instantaneous time encoding instead of the mean value encoding realized in the ASDM. This eliminates the effect of the dynamic range reduction of output pulses lengths, w... View full abstract»

• A Low-Power Incremental Delta–Sigma ADC for CMOS Image Sensors

Publication Year: 2016, Page(s):371 - 375
Cited by:  Papers (1)
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This brief presents a second-order incremental delta-sigma analog-to-digital converter (ADC) for CMOS image sensors (CISs). The ADC that employs a cascade of integrators with a feedforward architecture uses only one operational transconductance amplifier (OTA) by sharing the OTA between the first and second stages of the modulator. Further power and area savings are achieved by using a self-biasin... View full abstract»

• Energy-Efficient Associative Memory Based on Neural Cliques

Publication Year: 2016, Page(s):376 - 380
Cited by:  Papers (1)
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Traditional memories use an address to index the stored data. Associative memories rely on a different principle: Part of previously stored data are used to retrieve the remaining part. They are widely used, for instance, in network routers for packet forwarding. A classical way to implement such memories is content-addressable memory (CAM). Since its operation is fully parallel, the response is o... View full abstract»

• Efficient Circuit for Parallel Bit Reversal

Publication Year: 2016, Page(s):381 - 385
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Bit reversal is an essential part of the fast Fourier transform (FFT). However, compared to the amount of works on FFT architectures, far fewer works are dedicated to bit-reversal circuits until recent years. In this brief, the minimum latency and memory required for calculating the bit reversal of continuous-flow parallel data are formulated. The formulas are generic for all power of two parallel... View full abstract»

• Generalized Dissipativity Analysis of Digital Filters With Finite-Wordlength Arithmetic

Publication Year: 2016, Page(s):386 - 390
Cited by:  Papers (6)
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This brief investigates the generalized dissipativity of digital filters with finite-wordlength arithmetic. First, a new sufficient condition is proposed to guarantee the generalized dissipativity of single digital filters with finite-wordlength arithmetic. Unlike the existing works in the literature, this brief presents criteria for H∞ performance, l2 - l∞... View full abstract»

• Synchronization of Coupled Nonlinear Dynamical Systems: Interplay Between Times of Connectivity and Integral of Lipschitz Gain

Publication Year: 2016, Page(s):391 - 395
Cited by:  Papers (1)
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This brief considers the synchronization problem of coupled nonlinear dynamical systems over time-varying interaction graphs. We first show that infinite joint connectivity is necessary for achieving globally asymptotic synchronization. We then show that the commonly used Lipschitz condition on the nonlinear self-dynamics is not sufficient to ensure synchronization even for an arbitrarily large co... View full abstract»

• Nonideal Behavior of Analog Multipliers for Chaos Generation

Publication Year: 2016, Page(s):396 - 400
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In this brief, nonideal behaviors of analog multipliers are explicitly taken into account in the design of nonlinear electronic circuits. The nonidealities of the analog multipliers led to further nonlinear terms that, instead of being considered as parasitic effects, are here explicitly accounted for and exploited to generate new complex dynamics, including chaos. In fact, despite the accuracy of... View full abstract»

• Leader-Following Consensus of Discrete-Time Multiagent Systems With Encoding–Decoding

Publication Year: 2016, Page(s):401 - 405
Cited by:  Papers (6)
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The leader-following consensus of general linear discrete-time multiagent systems with a limited communication data rate and a directed fixed topology is investigated. The consensus protocol is designed for each agent, which is given in terms of states of its encoder and decoders with time-varying quantization levels. A rigorous analysis for the consensus convergence is provided. A finite lower bo... View full abstract»

• Periodic Event-Triggered Consensus With Quantization

Publication Year: 2016, Page(s):406 - 410
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This brief addresses the periodic event-triggered consensus problem for multiagent systems with quantized information communication over directed topology. The combined effect of periodic event-triggered control and quantized control on the consensus problem is investigated. Both the uniform and logarithmic quantizers are considered. Under the assumption that the communication topology has a direc... View full abstract»

• Introducing IEEE Collabratec

Publication Year: 2016, Page(s): 411
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• IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

Publication Year: 2016, Page(s): 412
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• IEEE Circuits and Systems Society Information

Publication Year: 2016, Page(s): C3
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Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org