# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 43

Publication Year: 2016, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2016, Page(s): C2
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• ### SRAM-Based Unique Chip Identifier Techniques

Publication Year: 2016, Page(s):1213 - 1222
Cited by:  Papers (3)
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Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent process-induced mismatch of SRAM cells. The proposed circuits improve upon those previously published by reducing the number of bits that vary from trial to trial, and... View full abstract»

• ### High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF( ${2}^{m}$ )

Publication Year: 2016, Page(s):1223 - 1232
Cited by:  Papers (4)
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This paper proposes an efficient pipelined architecture of elliptic curve scalar multiplication (ECSM) over GF(2m). The architecture uses a bit-parallel finite field (FF) multiplier accumulator (MAC) based on the Karatsuba-Ofman algorithm. The Montgomery ladder algorithm is modified for better sharing of execution paths. The data path in the architecture is well designed, so that the cr... View full abstract»

• ### Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling

Publication Year: 2016, Page(s):1233 - 1246
Cited by:  Papers (3)
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The recycling of electronic components has become a major industrial and governmental concern, as it could potentially impact the security and reliability of a wide variety of electronic systems. It is extremely challenging to detect a recycled integrated circuit (IC) that is already used for a very short period of time because the process variations outpace the degradation caused by aging, especi... View full abstract»

• ### Implementing Minimum-Energy-Point Systems With Adaptive Logic

Publication Year: 2016, Page(s):1247 - 1256
Cited by:  Papers (2)
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Timing-error-detection (TED)-based systems have been shown to reduce power consumption or increase yield due to reduced margins. This paper shows that the increased adaptability can be a great advantage in the system design in addition to the well-known mitigated susceptibility to ambient and internal variations. Specifically, the design tolerances of the power management are relaxed to enable eve... View full abstract»

• ### On Efficient Retiming of Fixed-Point Circuits

Publication Year: 2016, Page(s):1257 - 1265
Cited by:  Papers (1)
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Retiming of digital circuits is conventionally based on the estimates of propagation delays across different paths in the data-flow graphs (DFGs) obtained by discrete component timing model, which implicitly assumes that operation of a node can begin only after the completion of the operation(s) of its preceding node(s) to obey the data dependence requirement. Such a discrete component timing mode... View full abstract»

• ### Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Publication Year: 2016, Page(s):1266 - 1279
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This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static... View full abstract»

• ### Hybrid LUT/Multiplexer FPGA Logic Architectures

Publication Year: 2016, Page(s):1280 - 1292
Cited by:  Papers (2)
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Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Multiple hybrid configurable logic block architectures, both nonfracturable and fracturable with varying MUX:LUT logic element ratios are evaluated across two benchmark suites (VT... View full abstract»

• ### A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory

Publication Year: 2016, Page(s):1293 - 1304
Cited by:  Papers (4)
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Although Latin square is a well-known algorithm to construct low-density parity-check (LDPC) codes for satisfying long code length, high code-rate, good correcting capability, and low error floor, it has a drawback of large submatrix that the hardware implementation will be suffered from large barrel shifter and worse routing congestion in fitting NAND flash applications. In this paper, a top-down... View full abstract»

• ### A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing

Publication Year: 2016, Page(s):1305 - 1318
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Integral histogram image can accelerate the computing process of feature algorithm in computer vision, but exhibits high computation complexity and inefficient memory access. In this paper, we propose a configurable parallel architecture to improve the computing efficiency of integral histogram. Based on the configurable design in the architecture, multiple integral objects for integral histogram ... View full abstract»

• ### Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs

Publication Year: 2016, Page(s):1319 - 1332
Cited by:  Papers (1)
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Triple patterning lithography (TPL) is regarded as a promising technique to handle the manufacturing challenges in the 14nm technology node and beyond. It is necessary to consider TPL in early design stages to make the layout more TPL friendly and reduce the manufacturing cost. In this paper, we propose a flow to co-optimize cell layout decomposition and detailed placement. Our cell decomposition ... View full abstract»

• ### A 40-nm 16-Mb Contact-Programming Mask ROM Using Dual Trench Isolation Diode Bitcell

Publication Year: 2016, Page(s):1333 - 1341
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A 16-Mb mask read-only memory (ROM) chip based on a novel diode structure is proposed. The diodes are constructed by buried n-type implantation layer and heavily doped p-type diffusion layer. With dual-trench isolation process and borderless contact scheme, the diode array can realize ultrahigh density. The fabricated mask ROM chip using 40-nm CMOS bulk technology is wired with three levels of met... View full abstract»

• ### Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

Publication Year: 2016, Page(s):1342 - 1350
Cited by:  Papers (4)
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The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an average-8T SRAM based on an advanced technology, such a... View full abstract»

• ### Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture

Publication Year: 2016, Page(s):1351 - 1360
Cited by:  Papers (1)
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In this paper, we demonstrate an energy-reduction strategy that overcomes the stochastic switching characteristics of the spin-torque-transfer magnetic-RAM (STT-RAM) write operation and propose a write completion circuit needed for it. In contrast to the traditional worst case approach, which fixes the write duration for all cells, the proposed write technique terminates the write pulse after a wr... View full abstract»

• ### An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM

Publication Year: 2016, Page(s):1361 - 1370
Cited by:  Papers (4)
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Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual Vref sensing scheme (DVSS) that selectively uses an optimal Vref betwe... View full abstract»

• ### Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform

Publication Year: 2016, Page(s):1371 - 1376
Cited by:  Papers (1)
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In recent years, researchers have focused toward reduction in power dissipation and cell size to employ spin-transfer torque (STT) magnetic random-access memories (MRAMs) for embedded applications. Hence, the magnetic tunnel junctions (MTJs) with an optimized structure and magnetic properties are being explored to reduce the switching current. However, the switching current reduction in the MTJs g... View full abstract»

Publication Year: 2016, Page(s):1377 - 1390
Cited by:  Papers (1)
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In this paper, we propose a low-power technique, called RF power gating, which consists in varying the active time ratio (ATR) of the RF front end at a symbol time scale. This technique is especially well suited to adapt the power consumption of the receiver to the performance needs without changing its architecture. The effect of this technique on the bit error rate (BER) performances is studied ... View full abstract»

• ### Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers

Publication Year: 2016, Page(s):1391 - 1401
Cited by:  Papers (2)
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In this paper, we design a hardware and energy-efficient stochastic lower-upper decomposition (LUD) scheme for multiple-input multiple-output receivers. By employing stochastic computation, the complex arithmetic operations in LUD can be performed with simple logic gates. With proposed dual partition computation method, the stochastic multiplier and divider exhibit high computation accuracy with r... View full abstract»

• ### An All-Digital Gigahertz Class-S Transmitter in a 65-nm CMOS

Publication Year: 2016, Page(s):1402 - 1411
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A 65-nm all-digital Class-S transmitter with an entire digital frontend (DFE) and a current-mode Class-D (CMCD) power amplifier (PA) is presented. To realize the high operation rate and performance of the DFE, which includes a 1-bit band-pass ΣA modulator, a mixer, and interpolation filters, approaches, such as time-interleaving algorithm and modified Manchester encoding, are adopted. The m... View full abstract»

• ### Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization

Publication Year: 2016, Page(s):1412 - 1420
Cited by:  Papers (2)
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In orthogonal frequency-division multiplexing (OFDM) systems, integer frequency offset (IFO) causes a circular shift of the subcarrier indices in the frequency domain. The IFO can be mitigated through strict RF front-end design, which tends to be expensive, or by strictly limiting mobility and channel agility, which constrains operating scenarios. The IFO is, therefore, often estimated and removed... View full abstract»

• ### A Fully Integrated Point-of-Load Digital System Supply With PVT Compensation

Publication Year: 2016, Page(s):1421 - 1429
Cited by:  Papers (1)
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This paper presents a fully integrated process, supply voltage, and temperature compensated supply (PVTCS) for a point-of-load digital system. Through adding the appropriate weighted threshold voltage variation from the pMOS (ΔVTHP) and the nMOS (ΔVTHN) diodes to the reference voltage of a high-speed low-dropout voltage regulator, the supply of the digital circu... View full abstract»

• ### A Performance-Aware MOSFET Threshold Voltage Measurement Circuit in a 65-nm CMOS

Publication Year: 2016, Page(s):1430 - 1440
Cited by:  Papers (1)
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This paper presents a new performance-aware nanometer-scale MOSFET threshold voltage (VTH) measurement circuit that employs dual-segment nonlinear temperature compensation on the Brokaw circuit topology. Besides, a preregulator feedback control loop is used to enhance the power supply rejection (PSR) of the circuit. Fabricated in a UMC 65-nm CMOS process, it consumes 2.64 μW at 1.1 V supply... View full abstract»

• ### A 0.5 V 1.28-MS/s 4.68-fJ/Conversion-Step SAR ADC With Energy-Efficient DAC and Trilevel Switching Scheme

Publication Year: 2016, Page(s):1441 - 1449
Cited by:  Papers (1)
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This paper describes a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient trilevel alternate switching capacitive digital-to-analog converter (CDAC). The switching scheme of this CDAC preserves the features of the asymmetric-switching CDAC. By narrowing and smoothing the dynamic variation of DAC voltage, the switching scheme diminishes the dyn... View full abstract»

• ### A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta–Sigma Modulator

Publication Year: 2016, Page(s):1450 - 1459
Cited by:  Papers (1)
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A digital clock and data recovery (CDR) employing a time-dithered delta-sigma modulator (TDDSM) is presented. By enabling hybrid dithering of a sampling period as well as an output bit of the TDDSM, the proposed CDR enhances the resolution of digitally controlled oscillator, removes a low-pass filter in the integral path, and reduces jitter generation. Fabricated in a 65-nm CMOS process, the propo... View full abstract»

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu