# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Displaying Results 1 - 20 of 20

Publication Year: 2016, Page(s): C1
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2016, Page(s): C2
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• ### TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

Publication Year: 2016, Page(s):521 - 534
Cited by:  Papers (4)
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There are increasing concerns about possible malicious modifications of integrated circuits (ICs) used in critical applications. Such attacks are often referred to as hardware Trojans. While many techniques focus on hardware Trojan detection during IC testing, it is still possible for attacks to go undetected. Using a combination of new design techniques and new memory technologies, we present a n... View full abstract»

• ### End-to-End Latency Analysis of Dataflow Scenarios Mapped Onto Shared Heterogeneous Resources

Publication Year: 2016, Page(s):535 - 548
Cited by:  Papers (1)
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The design of embedded wireless and multimedia applications requires temporal analysis to verify if real-time constraints such as throughput and latency are met. This paper presents a design-time analytical approach to derive a conservative upper bound to the maximum end-to-end latency of a streaming application. Existing analytical approaches often assume static application models, which cannot c... View full abstract»

• ### Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications

Publication Year: 2016, Page(s):549 - 558
Cited by:  Papers (2)
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Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower pow... View full abstract»

• ### Wash Optimization and Analysis for Cross-Contamination Removal Under Physical Constraints in Flow-Based Microfluidic Biochips

Publication Year: 2016, Page(s):559 - 572
Cited by:  Papers (1)
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Recent advances in flow-based microfluidics have enabled the emergence of biochemistry-on-a-chip as a new paradigm in drug discovery, point-of-care disease diagnosis, and biomolecular recognition. However, these applications in biology and biochemistry require high precision to avoid erroneous assay outcomes and, therefore, are vulnerable to contamination between two fluidic flows with different b... View full abstract»

• ### Mapping for Maximum Performance on FPGA DSP Blocks

Publication Year: 2016, Page(s):573 - 585
Cited by:  Papers (6)
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The digital signal processing (DSP) blocks on modern field programmable gate arrays (FPGAs) are highly capable and support a variety of different datapath configurations. Unfortunately, inference in synthesis tools can fail to result in circuits that reach maximum DSP block throughput. We have developed a tool that maps graphs of add/sub/mult nodes to DSP blocks on Xilinx FPGAs, ensuring maximum t... View full abstract»

• ### Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults—From Device to Circuit Level

Publication Year: 2016, Page(s):586 - 597
Cited by:  Papers (1)
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This paper investigated the soft errors caused by particle strikes, such as high-energy neutrons, extending beyond the deep submicrometer era. Considering the structure of the layout and resulting nuclear reactions, multiple transient faults (MTFs) tend to be induced more frequently than do single transient faults (STFs), due to the effects of technology scaling. This means that the soft error rat... View full abstract»

• ### Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification

Publication Year: 2016, Page(s):598 - 610
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Extreme ultraviolet (EUV) flare and post-chemical mechanical polishing (CMP) metal thickness are two main manufacturability concerns that introduce critical dimension distortions in nanometer process technology. Dummification, the addition of dummy patterns, is an effective technique to address the two concerns. However, while the two dummification objectives are competing in nature, existing work... View full abstract»

• ### Joint Charge and Thermal Management for Batteries in Portable Systems With Hybrid Power Sources

Publication Year: 2016, Page(s):611 - 622
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This paper introduces a joint charge and thermal management problem for batteries in a battery-supercapacitor hybrid power source of a portable system, which has been equipped with a forced convection cooling technique, such as a fan. A key consideration in such a system is that the battery aging depends strongly on the battery temperature, which is in turn a function of the workload running on th... View full abstract»

• ### Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip

Publication Year: 2016, Page(s):623 - 636
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Self-heating and high-operating temperature are major concerns in 3-D-chip integration. In this paper, we leverage a 3-D test chip (WideIO dynamic random access memory on top of a logic die) equipped with temperature sensors and heaters to explore thermal effects and to develop advanced thermal modeling strategies suitable for complex 3-D-stacked circuits. We correlate temperature measurements wit... View full abstract»

• ### Multischedule Synthesis for Variant Management in Automotive Time-Triggered Systems

Publication Year: 2016, Page(s):637 - 650
Cited by:  Papers (1)
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Car manufacturers provide a growing variety of models and configuration options for customers. In the highly competitive and cost-driven automotive industry, managing these variants and increasing the reuse of functionality in different variants has therefore become one of the key challenges. This paper addresses the problem of generating variant schedules for time-triggered electrical/electronic-... View full abstract»

• ### Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction

Publication Year: 2016, Page(s):651 - 664
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On-chip dynamic random access memory (DRAM) cache has been recently employed in the memory hierarchy to mitigate the widening latency gap between high-speed cores and off-chip memory. Two important parameters are the DRAM cache miss rate (D$-MR) and the DRAM cache hit latency (D$-HL), as they strongly influence the performance. These parameters depend upon the DRAM set mapping policy. Recently pro... View full abstract»

• ### On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines

Publication Year: 2016, Page(s):665 - 678
Cited by:  Patents (1)
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Voltage droop is a major reliability concern in nano-scale very large-scale integration designs. Undesirable voltage droop is often a result of excessive IR drop. On the other hand, Ldi/dt-induced droop occurs when logic gates in the circuit draw high-switching current from the on-chip power supply network, and this problem is exacerbated at high-clock frequencies and smaller technology nodes. A c... View full abstract»

• ### TSV Extracted Equivalent Circuit Model and an On-Chip Test Solution

Publication Year: 2016, Page(s):679 - 690
Cited by:  Papers (1)
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Through silicon via (TSV) is the enabling technology for 3-D integrated circuit (IC) realization. To develop manufacturing tests for 3-D ICs, TSV has to be accurately modeled. Analytical methods are commonly used to develop circuit models for TSVs. These models are often difficult to develop and require some assumptions to simplify the problem. This paper presents a new method utilizing computer-a... View full abstract»

• ### An Endurance-Aware Metadata Allocation Strategy for MLC NAND Flash Memory Storage Systems

Publication Year: 2016, Page(s):691 - 694
Cited by:  Papers (7)
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This paper presents a reliability-aware metadata allocation strategy called scatter-single-level cell (SLC) for multiple-level cell (MLC) NAND flash memory storage systems. In scatter-SLC, metadata is kept in least significant bit (LSB) pages and corresponding most significant bit (MSB) pages are bypassed. Without partitioning SLC and MLC blocks, scatter-SLC can eliminate the unbalanced lifetime b... View full abstract»

• ### Introducing IEEE Collabratec

Publication Year: 2016, Page(s): 695
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• ### IEEE Access

Publication Year: 2016, Page(s): 696
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2016, Page(s): C3
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

Publication Year: 2016, Page(s): C4
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## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu