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IEEE Design & Test

Issue 2 • April 2016

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Displaying Results 1 - 21 of 21
  • Front Cover

    Publication Year: 2016, Page(s): C1
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  • Cover 2

    Publication Year: 2016, Page(s): C2
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  • IEEE Design & Test of Computers publication information

    Publication Year: 2016, Page(s): 1
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  • Table of Contents

    Publication Year: 2016, Page(s):2 - 3
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  • Three-Dimensional Integrated Circuits

    Publication Year: 2016, Page(s):4 - 6
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  • Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools—Part 2

    Publication Year: 2016, Page(s):7 - 8
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  • Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects

    Publication Year: 2016, Page(s):9 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    Detection of delay faults in 3-D interconnects is crucial for building reliable 3-D ICs. This paper presents a test methodology based on a globalring structure with a variable output thresholding technique to detect delay faults in multipin 3-D interconnects in multidie 3-D ICs. The proposed test architecture with an enhanced clock period measurement circuit detects delay faults in multipin 3-D in... View full abstract»

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  • High-Frequency Temperature-Dependent Through-Silicon-Via (TSV) Model and High-Speed Channel Performance for 3-D ICs

    Publication Year: 2016, Page(s):17 - 29
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1313 KB)

    Noise coupling through the substrate or silicon interposer among adjacent TSVs has a significant impact on the signal integrity of the TSVs. Since resistance and capacitance are dependent on temperature, more accurate electrical models for TSVs should incorporate the temperature dependency of the material. This paper presents high-frequency temperature-dependent RLGC models for two neighboring TSV... View full abstract»

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  • Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

    Publication Year: 2016, Page(s):30 - 39
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1085 KB)

    Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channel-based 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than ... View full abstract»

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  • Thermoelectric Codesign of 3-D CPUs and Embedded Microfluidic Pin-Fin Heatsinks

    Publication Year: 2016, Page(s):40 - 48
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (887 KB)

    Microfluidic cooling is considered an effective cooling method suitable for 3-D ICs. However, TSVs are placed in pin fins and coolant flows in between pin fins, so inserting more pin fins to increase the vertical bandwidth reduces the cooling capacity. This paper codesigns 3-D CPU architectures and microfluidic heatsinks to simultaneously optimize the performance and cooling capacity of 3-D ICs wi... View full abstract»

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  • An Optimization Platform for Digital Predistortion of Power Amplifiers

    Publication Year: 2016, Page(s):49 - 58
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1304 KB)

    The article introduces an integrated hardware/software codesign and test platform for the digital predistortion and power amplifier blocks of radiofrequency transceivers. The platform allows evaluation and optimization of system performance with minimum computational resources, contributing to higher design flexibility. The platform is demonstrated on a variety of power amplifiers. View full abstract»

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  • Variability and Reliability Awareness in the Age of Dark Silicon

    Publication Year: 2016, Page(s):59 - 67
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (906 KB)

    Ability to supply more transistors per chip is outpacing improvements in cooling and power delivery. The result is operation that selectively powers on or off subsets of transistors. This paper suggests innovate ways to take advantage of the consequent “dark” silicon to meet a pair of additional emerging challenges-reliability and tolerance of variability. View full abstract»

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  • Energy-Efficient Computing in Nanoscale CMOS

    Publication Year: 2016, Page(s):68 - 75
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (783 KB)

    This Perspectives paper is on the ever-interesting topic of energy-efficient computing. It shows us that future goals are orders of magnitude higher energy efficiency (measured in Joule per operation) and a means to achieve that is operating at near-threshold voltage. View full abstract»

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  • The Changing Computing Paradigm With Internet of Things: A Tutorial Introduction

    Publication Year: 2016, Page(s):76 - 96
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (993 KB)

    This Tutorial paper is about the Internet of Things, its applications, challenges, and how it may change the way of computing. Besides a comprehensive introduction, it focuses on two major design constraints, namely, security and power management. View full abstract»

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  • Report of the 2015 Embedded Systems Week (ESWEEK)

    Publication Year: 2016, Page(s):97 - 98
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  • CEDA Currents

    Publication Year: 2016, Page(s):99 - 100
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  • Test Technology TC Newsletter

    Publication Year: 2016, Page(s):101 - 102
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  • My IEEE

    Publication Year: 2016, Page(s): 103
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  • The Five Stages of Project Grief

    Publication Year: 2016, Page(s): 104
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  • Cover 3

    Publication Year: 2016, Page(s): C3
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  • Cover 4

    Publication Year: 2016, Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

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Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)