# IEEE Transactions on Computers

## Filter Results

Displaying Results 1 - 25 of 26
• ### Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

Publication Year: 2016, Page(s):677 - 678
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• ### Non-Blocking Testing for Network-on-Chip

Publication Year: 2016, Page(s):679 - 692
Cited by:  Papers (3)
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To achieve high reliability in on-chip networks, it is necessary to test the network as frequently as possible to detect physical failures before they lead to system-level failures. A main obstacle is that the circuit under test has to be isolated, resulting in network cuts and packet blockage which limit the testing frequency. To address this issue, we propose a comprehensive network-level approa... View full abstract»

• ### Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs

Publication Year: 2016, Page(s):693 - 705
Cited by:  Papers (1)
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TSV-to-TSV coupling is known to be a significant detriment to signal integrity in three-dimensional (3D) IC architectures. Designing a reliable Through-Silicon Via is critical in order to support better performance. This paper explores the challenges brought on by capacitive and inductive TSV-to-TSV coupling in TSV-based 3D ICs. Based on our analyses, we propose two approaches to mitigate these ef... View full abstract»

• ### Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults

Publication Year: 2016, Page(s):706 - 715
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Feedback bridging faults may give rise to oscillations within integrated circuits. This work mainly investigates the propagation of oscillations, a behavior that may have a relevant impact on the fault detection. We propose both a logic-level model of the faulty circuit and two techniques aiming to the generation of high-quality test sequences. View full abstract»

• ### CoreRank: Redeeming “Sick Silicon” by Dynamically Quantifying Core-Level Healthy Condition

Publication Year: 2016, Page(s):716 - 729
Cited by:  Papers (1)
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In field degradation of manycore processors poses a grand challenge to core management, largely because the degradation is hard to quantify. We propose a novel core-level degradation quantification scheme, CoreRank, to facilitate the management. We first develop a new degradation metric, called “healthy condition”, to capture the implication of performance degradation of a core with ... View full abstract»

• ### A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures

Publication Year: 2016, Page(s):730 - 743
Cited by:  Papers (3)
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Aggressive technology scaling triggers novel challenges to the design of multi-/many-core systems, such as limited power budget and increased reliability issues. Today's many-core systems employ dynamic power management and runtime mapping strategies trying to offer optimal performance while fulfilling power constraints. On the other hand, due to the reliability challenges, online testing techniqu... View full abstract»

• ### Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

Publication Year: 2016, Page(s):744 - 754
Cited by:  Papers (5)
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Software-Based Self-Test is an effective methodology for devising the online testing of Systems-on-Chip. In the automotive field, a set of test programs to be run during mission mode is also called Core Self-Test library. This paper introduces many new contributions: (1) it illustrates the several issues that need to be taken into account when generating test programs for on-line execution; (2) it... View full abstract»

• ### Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Publication Year: 2016, Page(s):755 - 769
Cited by:  Papers (1)
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Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high... View full abstract»

• ### A Local Parallel Search Approach for Memory Failure Pattern Identification

Publication Year: 2016, Page(s):770 - 780
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Due to more aggressive design rules adopted by memories than logic circuits, memories have been considered as the major technology driver of advanced logic circuits, so far as CMOS process technology is concerned. Memory failure pattern identification therefore is important, and is traditionally considered a key task that can help improve the efficiency of memory diagnosis and failure analysis. Cr... View full abstract»

• ### A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

Publication Year: 2016, Page(s):781 - 790
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This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. A soft... View full abstract»

• ### Evaluation and Mitigation of Radiation-Induced Soft Errors in Graphics Processing Units

Publication Year: 2016, Page(s):791 - 804
Cited by:  Papers (8)
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Graphics processing units (GPUs) are increasingly attractive for both safety-critical and High-Performance Computing applications. GPU reliability is a primary concern for both the automotive and aerospace markets and is becoming an issue also for supercomputers. In fact, the high number of devices in large data centers makes the probability of having at least a device corrupted to be very high. I... View full abstract»

• ### A Framework for Truthful Online Auctions in Cloud Computing with Heterogeneous User Demands

Publication Year: 2016, Page(s):805 - 818
Cited by:  Papers (10)
| | PDF (939 KB) | HTML

Auction-style pricing policies can effectively reflect the underlying trends in demand and supply for the cloud resources, and thereby attracted a research interest recently. In particular, a desirable cloud auction design should be (1) online to timely reflect the fluctuation of supply-demand relations, (2) expressive to support the heterogeneous user demands, and (3) truthful to discourage users... View full abstract»

• ### A Holistic Approach Towards Intelligent Hotspot Prevention in Network-on-Chip-Based Multicores

Publication Year: 2016, Page(s):819 - 833
Cited by:  Papers (1)
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Traffic hotspots, a severe form of network congestion, can be caused unexpectedly in a network-on-chip (NoC) due to the immanent spatio-temporal unevenness of application traffic. Hotspots reduce the NoC's effective throughput, where in the worst-case scenario, network traffic flows can be frozen indefinitely. To alleviate this problematic phenomenon several adaptive routing algorithms employ onli... View full abstract»

• ### Analysis and Design of Real-Time Servers for Control Applications

Publication Year: 2016, Page(s):834 - 846
Cited by:  Papers (2)
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Today, a considerable portion of embedded systems, e.g., automotive and avionic, comprise several control applications. Guaranteeing the stability of these control applications in embedded systems, or cyber-physical systems, is perhaps the most fundamental requirement while implementing such applications. This is different from the classical hard real-time systems where often the acceptance criter... View full abstract»

• ### Building Expressive and Area-Efficient Directories with Hybrid Representation and Adaptive Multi-Granular Tracking

Publication Year: 2016, Page(s):847 - 859
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Mainstream chip multiprocessors already include a significant number of cores that make straightforward snooping-based cache coherence less appropriate. Further increase in core count will almost certainly require more sophisticated tracking of data sharing to minimize unnecessary messages and cache snooping. Directory-based coherence has been the standard solution for large-scale shared-memory mu... View full abstract»

• ### Dynamic Hardware Monitors for Network Processor Protection

Publication Year: 2016, Page(s):860 - 872
Cited by:  Papers (1)
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The importance of the Internet for society is increasing. To ensure a functional Internet, its routers need to operate correctly. However, the need for router flexibility has led to the use of software-programmable network processors in routers, which exposes these systems to data plane attacks. Recently, hardware monitors have been introduced into network processors to verify the expected behavio... View full abstract»

• ### Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies

Publication Year: 2016, Page(s):873 - 887
| | PDF (1667 KB) | HTML

Routing algorithm design for on-chip networks (OCNs) has become increasingly challenging due to high levels of integration and complexity of modern systems-on-chip (SoCs). The inherent unreliability of components, embedded oversized IP blocks, and finegrained voltage-frequency islands (VFIs) management among others, raise several challenges in OCNs: (a) network topologies become irregular or asymm... View full abstract»

• ### Focus and Shoot: Exploring Auto-Focus in RFID Tag Identification Towards a Specified Area

Publication Year: 2016, Page(s):888 - 901
Cited by:  Papers (4)
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With the rapid proliferation of RFID technologies, RFID has been introduced into applications such as inventory and sampling inspection. Conventionally, in RFID systems, the reader usually identifies all the RFID tags in the interrogation region with the maximum power. However, some applications may only need to identify the tags in a specified area, which is usually smaller than the reader's defa... View full abstract»

• ### ForestDB: A Fast Key-Value Storage System for Variable-Length String Keys

Publication Year: 2016, Page(s):902 - 915
Cited by:  Papers (3)
| | PDF (1852 KB) | HTML

Indexing key-value data on persistent storage is an important factor for NoSQL databases. Most key-value storage engines use tree-like structures for data indexing, but their performance and space overhead rapidly get worse as the key length becomes longer. This also affects the merge or compaction cost which is critical to the overall throughput. In this paper, we present ForestDB, a key-value st... View full abstract»

• ### $MARS$ : Mobile Application Relaunching Speed-Up through Flash-Aware Page Swapping

Publication Year: 2016, Page(s):916 - 928
Cited by:  Papers (4)
| | PDF (1601 KB) | HTML

The approach for fast application relaunching on the current Android system is to cache background applications in memory. This mechanism is limited by the available memory size. In addition, the application state may not be easily recovered. We propose a prototype system, MARS, to enable page swapping and cache more applications. MARS can speed up the application relaunching and restore the appli... View full abstract»

• ### Near-Optimal One-Sided Scheduling for Coded Segmented Network Coding

Publication Year: 2016, Page(s):929 - 939
Cited by:  Papers (4)
| | PDF (694 KB) | HTML

As a variation of random linear network coding, segmented network coding (SNC) has attracted great interest in data dissemination over lossy networks due to its low computational cost. In order to guarantee the success of decoding, SNC can adopt a feedbackless forward error correction (FEC) approach by applying a linear block code to the input packets before segmentation at the source node. In par... View full abstract»

• ### Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

Publication Year: 2016, Page(s):940 - 951
Cited by:  Papers (6)
| | PDF (1273 KB) | HTML

Spin-transfer torque RAM (STT-RAM) has emerged as an energy-efficient and high-density alternative to SRAM for large on-chip caches. However, its high write energy has been considered as a serious drawback. Hybrid caches mitigate this problem by incorporating a small SRAM cache for write-intensive data along with an STT-RAM cache. In such architectures, choosing cache blocks to be placed into the ... View full abstract»

• ### Trust Evaluation in Online Social Networks Using Generalized Network Flow

Publication Year: 2016, Page(s):952 - 963
Cited by:  Papers (13)
| | PDF (1116 KB) | HTML Media

In online social networks (OSNs), to evaluate trust from one user to another indirectly connected user, the trust evidence in the trusted paths (i.e., paths built through intermediate trustful users) should be carefully treated. Some paths may overlap with each other, leading to a unique challenge of path dependence, i.e., how to aggregate the trust values of multiple dependent trusted paths. OSNs... View full abstract»

• ### Unfaithful Glitch Propagation in Existing Binary Circuit Models

Publication Year: 2016, Page(s):964 - 978
| | PDF (1088 KB) | HTML Media

We show that no existing continuous-time, binary value-domain model for digital circuits is able to correctly capture glitch propagation. Prominent examples of such models are based on pure delay channels (P), inertial delay channels (I), or the elaborate Delay Degradation Model (DDM) channels proposed by Bellido-Diaz et al. We accomplish our goal by considering the border between solvability and ... View full abstract»

• ### Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors

Publication Year: 2016, Page(s):979 - 991
Cited by:  Papers (1)
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With increasing transistor density on a single chip, processor design in the nanoscale era is hitting power and frequency walls. Due to these challenges, processors not only need to run fast, but remain cool and consume less energy. At this juncture where no further improvement in clock frequency is possible, data dependent latching through timing speculation provides a silver lining. In this pape... View full abstract»

## Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org