# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 61

Publication Year: 2016, Page(s):C1 - 530
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2016, Page(s): C2
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• ### Area-Efficient and Low-Leakage Diode String for On-Chip ESD Protection

Publication Year: 2016, Page(s):531 - 536
Cited by:  Papers (6)
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Diode string was used as the effective on-chip electrostatic discharge (ESD) protection device. To reduce the leakage current and the layout area, an area-efficient and low-leakage diode string is proposed in this paper. The standard steps of P- implantation and silicide blocking in CMOS process are used in this design to realize the proposed diode string with stacked P-/N+ diodes. The test device... View full abstract»

• ### Quantum Transport Analysis of Conductance Variability in Graphene Nanoribbons With Edge Defects

Publication Year: 2016, Page(s):537 - 543
Cited by:  Papers (1)
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We study the influence of edge defects and the downscaling of graphene nanoribbon (GNR) width (W) on the ON- and OFF-state conductance (GON and GOFF) and the ON-OFF conductance ratio (GON/GOFF). The averaged properties and the variability are explored by simulating ensembles of defected GNRs with various percentages of edge defects using atomistic quantu... View full abstract»

• ### First Principles Calculations of Bonding and Charges at the Al2 Interface in a c-Si/SiO2O3Interface in a c-Si/SiO2/am-Al2O3 Structure Applicable for the Surface Passivation of Silicon-Based Solar Cells

Publication Year: 2016, Page(s):544 - 550
Cited by:  Papers (3)
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We present the electronic properties of the crystalline-silicon (c-Si)/SiO2/am-Al2O3 interface using first principles calculations. First, we generate a relaxed 3×1 supercell of amorphous (am)-Al2O3, which we use as a benchmark structure, validated through the experimental data. Next, using this, we generate a relaxed supercell of the c... View full abstract»

• ### Channel Profile Design of $\text{E}\delta$ DC MOSFET for High Intrinsic Gain and Low $V_{T}$ Mismatch

Publication Year: 2016, Page(s):551 - 557
Cited by:  Papers (2)
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In this paper, we present a systematic procedure for the design of a channel profile of an epitaxial delta doped channel (EδDC) MOS transistor so that the intrinsic gain (Au) is high and the threshold voltage (VT) mismatch is low. Analytical study shows that a tradeoff relation exists between low VT mismatch and high AV with respect to the thickne... View full abstract»

• ### Impact of Postdeposition Annealing Ambient on the Mobility of Ge nMOSFETs With 1-nm EOT Al2O3/GeOx/Ge Gate-Stacks

Publication Year: 2016, Page(s):558 - 564
Cited by:  Papers (1)
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The impact of postdeposition annealing (PDA) ambient on electrical properties of thin equivalent oxide thickness (EOT) Al2O3/GeOx/Ge gate-stacks is investigated. It is found that the surface states inside the conduction band of Ge are significantly suppressed by 40% through PDA with atomic deuterium ambient. As a result, enhancement of the effective mobility in the... View full abstract»

• ### Capacitance Modeling in Dual Field-Plate Power GaN HEMT for Accurate Switching Behavior

Publication Year: 2016, Page(s):565 - 572
Cited by:  Papers (4)
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In this paper, a surface-potential-based compact model is proposed for the capacitance of an AlGaN/GaN high-electron mobility transistor (HEMT) dual field-plate (FP) structure, i.e., with gate and source FPs. FP incorporation in a HEMT gives an improvement in terms of enhanced breakdown voltage, reduced gate leakage, and so on, but it affects the capacitive nature of the device, particularly by br... View full abstract»

• ### Dual-Gate MoS2 FET With a Coplanar-Gate Engineering

Publication Year: 2016, Page(s):573 - 577
Cited by:  Papers (1)
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A dual-gate multilayer MoS2 FET with a standard backside gate and a nonstandard coplanar top gate is demonstrated and analyzed. The special feature of this device is that the gate and MoS2 channel can be directly coupled on the same plane through the bottom-conducting Si substrate. The coplanar-gate MoS2 FET shows a good performance with a large ON-OFF ratio (ION/O... View full abstract»

• ### Controlling 4H–SiC Schottky Barriers by Molybdenum and Molybdenum Nitride as Contact Materials

Publication Year: 2016, Page(s):578 - 583
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In this paper, Schottky diodes, consisting of an n-doped 4H-silicon carbide substrate, and molybdenum and molybdenum nitride thin-film metallization, are presented. By the variation of the nitrogen amount in the molybdenum nitride thin films, we successfully manage to adjust the effective Schottky barrier height in the range 0.68-1.03 eV at room temperature. In addition, the temperature dependence... View full abstract»

• ### RF Characterization of Vertical Wrap-Gated InAs/High- $kappa$ Nanowire Capacitors

Publication Year: 2016, Page(s):584 - 589
Cited by:  Papers (6)
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This paper presents RF as well as low-frequency capacitance-voltage (C-V) characterization of vertical wrap-gated InAs/high-κ nanowire MOS capacitors. A full equivalent circuit model for traps is used to fit the low-frequency C-V characteristics, from which the interface trap density (Dit) and border trap density (Nbt) are evaluated separately. The results show compara... View full abstract»

• ### Measurement of Temperature in GaN HEMTs by Gate End-to-End Resistance

Publication Year: 2016, Page(s):590 - 597
Cited by:  Papers (5)
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We have used the gate end-to-end (GEE) resistance method to measure channel temperatures in GaN HEMTs. This method is appealing for its simplicity and sensitivity to temperature immediately adjacent to the base of the gate, where several important degradation mechanisms occur. This region is not normally accessible with optical measurement techniques, due to shadowing by the gate and field plate o... View full abstract»

• ### Trapping Effects at the Drain Edge in 600 V GaN-on-Si HEMTs

Publication Year: 2016, Page(s):598 - 605
Cited by:  Papers (3)
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In this paper, we investigate the influence of the drain electrode on the dynamic switching behavior of AlGaN/GaN high-electron-mobility transistors on Si substrate. By adding a field plate to the drain electrode, a dramatic increase in the dynamic ON-resistance dynRON was identified. The dispersion effect is correlated with the high electric field below the drain field plate (DFP), the... View full abstract»

• ### The III-Nitride Double Heterostructure Revisited: Benefits for Threshold Voltage Engineering of MIS Devices

Publication Year: 2016, Page(s):606 - 613
Cited by:  Papers (1)
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GaN-based devices are seen as ideal candidates for power-switching applications. For the acceptance of GaN-based devices by module designers, obtaining enhancement-mode (e-mode) behavior in GaN-based heterostructure field-effect transistors (HFETs) has long been in the focus. Although the gate-injection approach appears to be the most promising one to achieve e-mode devices, using a double heteros... View full abstract»

• ### Normally OFF GaN-on-Si MIS-HEMTs Fabricated With LPCVD-SiNx Passivation and High-Temperature Gate Recess

Publication Year: 2016, Page(s):614 - 619
Cited by:  Papers (6)
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Low-current-collapse normally OFF GaN-on-Si MIS high-electron-mobility transistors (MIS-HEMTs) are fabricated with low-pressure chemical-vapor-deposited SiNx (LPCVD-SiNx) passivation and high-temperature low-damage gate-recess technique. The high-thermal-stability LPCVD-SiNx enables a passivation-prior-to-ohmic process strategy and effectively suppresses deep state... View full abstract»

• ### Bonding Pad Over Active Structure for Chip Shrinkage of High-Power AlGaN/GaN HFETs

Publication Year: 2016, Page(s):620 - 624
Cited by:  Papers (1)
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This paper reports a bonding pad over active (BPOA) structure with photosensitive polyimide (PSPI) as the intermetal dielectric layer to reduce the chip size of high-power enhancement-mode AlGaN/GaN heterojunction FETs (HEFTs) on a 150-mm (6-in) Si substrate. The fabricated AlGaN/GaN HFETs with a BPOA structure exhibited a threshold voltage and a maximum current of 0.6 V and 38.6 A, respectively, ... View full abstract»

• ### Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications

Publication Year: 2016, Page(s):625 - 630
Cited by:  Papers (3)
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For the first time, we comprehensively evaluate 6T SRAM stability and performance using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on the ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent device electrostatics and superior stability, the monolayer TMD is favored for low-power SRAM applications, while the bilayer TMD, with higher carrier mobility, is m... View full abstract»

• ### Circuit Models for Ferroelectrics—Part I: Physics of Polarization Switching

Publication Year: 2016, Page(s):631 - 636
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We present a physical circuit model of ferroelectric (FE) polarization switching for the analysis and design of hybrid FE-CMOS circuits. Stochastic geometry is applied to domain nucleation, growth, and coalescence under arbitrary voltage and current input signals. The circuit model is first constructed for ideal FE capacitors and then extended to the realistic effects of lateral scaling, anisotrop... View full abstract»

• ### Circuit Models for Ferroelectrics—Part II: Analysis of FE-Nonvolatile Latches

Publication Year: 2016, Page(s):637 - 642
Cited by:  Papers (2)
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We present a detailed analysis of hybrid ferroelectric (FE)-CMOS nonvolatile latches, based on simulations with the unified physical circuit model from Part-I and experimental verification with circuit measurements. Hybrid FE-CMOS latches are categorized into three classes by the circuit topology of the readout operation. The effect of the physical model parameters is studied in all regions of ope... View full abstract»

• ### A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs

Publication Year: 2016, Page(s):643 - 651
Cited by:  Papers (1)
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In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage (Vmin View full abstract»

• ### Compact Modeling of Magnetic Tunneling Junctions

Publication Year: 2016, Page(s):652 - 658
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We present a simple, yet physical compact model of a magnetic tunnel junction that captures relevant physical effects needed for a realistic memory design and proposes an accurate noise simulation method that can be implemented in a circuit simulator without introducing additional nodes. We also discuss the limitations of existing compact modeling approaches. View full abstract»

• ### Accurate Lifetime Estimation of Sub-20-nm NAND Flash Memory

Publication Year: 2016, Page(s):659 - 667
Cited by:  Papers (2)
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Previously, we developed a charge loss/gain model for NAND flash memory, which is taking into account various failure mechanisms. In addition, we extracted all the parameters of the new model in the highest (PV3) and lowest states (ERS). In this paper, however, the physical information for the parameters and the whole procedure of the parameter extraction are covered in detail. We also extracted t... View full abstract»

• ### Improved Short-Channel Characteristics With Long Data Retention Time in Extreme Short-Channel Flash Memory Devices

Publication Year: 2016, Page(s):668 - 674
Cited by:  Papers (2)
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Owing to the scaling demands, source/drain (S/D) junction engineering has evolved as a promising technique to improve the performance and reliability of NAND flash memory devices. In this paper, we investigate the impact of S/D doping lateral straggle σL on the program characteristics, data retention, and short-channel effects (SCEs) for sub-25-nm NAND flash memory device. Here, we consider... View full abstract»

• ### A Compact Model for Single-Poly Multitime Programmable Memory Cells

Publication Year: 2016, Page(s):675 - 683
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A compact model for the single-poly multitime programmable (MTP) memory cells is presented in this paper for the first time. It is based on the charge balance approach, while the traditional old model is on the fixed capacitive coupling approach. The proposed cell model has been implemented by Verilog-A and integrated into commercial SPICE simulator. The model supports both dc and transient analys... View full abstract»

• ### Noise Margin Modeling for Zero- $V_{\text {GS}}$ Load TFT Circuits and Yield Estimation

Publication Year: 2016, Page(s):684 - 690
Cited by:  Papers (1)
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The flexible electronics is promising in the area of the Internet of Things and wearable devices and the thin-film transistor (TFT) technologies are crucial for flexible electronics. Among them, the zero-VGS load TFT circuits are widely used for its simple structure and high gain merits. However, the yield model is lacking for zero-VGS load TFT circuits. In this paper, the an... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy