By Topic

Solid-State Circuits, IEEE Journal of

Issue 8 • Date Aug 1994

Filter Results

Displaying Results 1 - 25 of 26
  • Smart sensor interface with A/D conversion and programmable calibration

    Publication Year: 1994 , Page(s): 963 - 966
    Cited by:  Papers (21)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    In this paper we present a new architecture for a smart sensor interface. It is based on an oversampled A/D converter associated with a small ROM containing calibration coefficients. The nonlinear function desired is obtained by piecewise linear interpolation between the values stored in the ROM, without any additional circuits. This solution has the advantage of high programming flexibility, long-term stability, and low area consumption. Moreover, it is suitable for co-integration with sensors because of its minimum analog content. A prototype was integrated in a CMOS 1.2-μm technology. Simulation and experimental results are reported together with a detailed theoretical analysis and some design guidelines View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-frequency and high-resolution fourth-order ΣΔ A/D converter in BiCMOS technology

    Publication Year: 1994 , Page(s): 857 - 865
    Cited by:  Papers (22)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB)  

    A high-performance cascaded sigma-delta modulator is presented. It has a new three-stage fourth-order topology and provides functionally a maximum signal to quantization noise ratio of 16 bits and 16.5-bit dynamic range with an oversampling ratio of only 32. This modulator is implemented with fully differential switch-capacitor circuits and is manufactured in a 2-μm BiCMOS process. The converter, operated from +/-2.5 V power supply, +/-1.25 V reference voltage and oversampling clock of 48 MHz, achieves 97 dB resolution at a Nyquist conversion rate of 1.5 MHz after comb-filtering decimation. The power consumption of the converter is 180 mW. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOS

    Publication Year: 1994 , Page(s): 866 - 872
    Cited by:  Papers (29)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB)  

    A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-μm CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm2 and the core of the parallel ADC array occupies an area of 2.7×3.3 mm2. The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 10-bit pipelined switched-current A/D converter

    Publication Year: 1994 , Page(s): 967 - 971
    Cited by:  Papers (24)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB)  

    A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm2 . The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 25-Ms/s 8-bit CMOS A/D converter for embedded application

    Publication Year: 1994 , Page(s): 879 - 886
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    The design of an 8-bit CMOS A/D converter is described which is intended for embedded operation in VLSI chips for video applications. The requirements on accuracy are analyzed and a comparator circuit is shown which realizes a high bandwidth. The full-flash architecture operates on wideband signals like CVBS in television systems. The A/D converter core measures 2.8 mm2 in a 1 μm CMOS process. The embedded operation of the A/D converter is illustrated on a video line-resizing chip View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A monolithic quad line driver for industrial applications

    Publication Year: 1994 , Page(s): 957 - 962
    Cited by:  Papers (10)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    The device described in this paper is a new quad line driver to be used in the hostile and noisy industrial environment and developed in mixed technology (BCD: Bipolar, CMOS, DMOS). It consists of four independent line drivers, each of which has a rail-to-rail push-pull output stage realized with power DMOS transistors connected in half bridge configuration. Even though the device is designed to be used primarily in the output cards of programmable controllers, it is a general purpose device, since it can drive any kind of load (resistive, capacitive, or inductive) with an output current of 100 mA. The novel structure of the top driver allows full protection of the output stage against any kind of short circuits and/or overloads, providing a linear current limitation. Furthermore, when a channel is tristated, for every applied voltage ranging from ground to the supply voltage, virtually zero current is absorbed from the output. An innovative high efficiency central charge pump circuit has also been designed and implemented, making both a very wide supply voltage operation (6-50 V) and high switching frequency (up to 500 KHz) possible, The device can also be used as a receiver since the input voltage can swing from -10-50 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages

    Publication Year: 1994 , Page(s): 936 - 942
    Cited by:  Papers (126)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from the standard switched-capacitor technique, is presented. It is called switched-opamp because it is based on the replacement of the critical switches with opamps which are turned on and off. This technique results in a true, very low voltage operation without the need for voltage multipliers. As an example, a second order lowpass switched-capacitor filter is implemented in the switched-opamp technique. This filter operates with only a 1.5 V power supply. It is realized in a 2.4-μm CMOS process with VT=±0.9 V. It has a measured total harmonic distortion of -60 dB for a signal swing of 600 mVptp and a powerdrain of only 110 μW View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A laser control chip combining a power regulator and a 622-Mbit/s modulator

    Publication Year: 1994 , Page(s): 947 - 951
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    This paper presents a circuit combining a 622-Mbit/s laser diode modulator and a power regulator with a closed loop bandwidth of less than 100 Hz. The power regulator's closed loop bandwidth is implemented using an integrator configuration employing a current division technique to implement a large integration resistor, and an electronic time-constant enhancement technique to achieve the desired closed loop bandwidth. Impacts of the electronic time-constant enhancement technique on noise performance are discussed. The power regulator includes an output stage capable of delivering the needed bias current for the laser diode. The output stage is implemented as a high-ratio bipolar current mirror using an area-efficient topology. The modulator has ECL-compatible inputs including 50-Ω input termination resistors, and it can modulate the laser diode with a current of up to 45 mApp View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 4/7 kHz audio bandwidth selectable digital phone interface (DPI) chip with on-chip analog functions and modem

    Publication Year: 1994 , Page(s): 914 - 920
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    The Digital Phone Interface (DPI) is designed for a new generation of digital telephone terminals for private exchanges, This circuit gives a total solution for all telephone functions, thereby including DSP functions, voice coding/decoding and analog front end, signal generators for DTMF and ringing, a modem for data transfer between terminal and exchange and a multitude of interfaces to communicate to the external world. Besides the normal earpiece micro and speaker, handsfree operation is available by using a selectable input low-noise microphone amplifier and an additional 50 Ω mWLS driver. For the handsfree operation, a digital AGC and anti-oscillation (anti-larsen) function is implemented. The line modem generates a modified RTZ (WAL2) code and is able to cover distances up to 1.5 km. In addition, the component is extensible with external signal processing modules (echo cancelling) and is also able to transfer a 7 kHz speech bandwidth. The device is a mixed analog/digital design produced in a 1.2 μm CMOS technology on 46 mm 2 die area and consumes 200 mW View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's

    Publication Year: 1994 , Page(s): 887 - 894
    Cited by:  Papers (7)  |  Patents (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB)  

    A two-dimensional power-line selection scheme for an iterative CMOS circuit block is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks in a two-dimensional arrangement and selectively energized by two-dimensional power-line selection. It is shown to be suitable for dual word-line structure, particularly because of its single sub-word line activation. This scheme achieves a very large reduction of active current to one sixteenth, from 116 mA to 22 mA for a 1-V 16-Gb DRAM with dual word-line structure, while maintaining a speed comparable to existing multi-megabit DRAM's. The proposed scheme is promising for reducing the active power of future multi-gigabit DRAM's View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An experimental high-density DRAM cell with a built-in gain stage

    Publication Year: 1994 , Page(s): 978 - 981
    Cited by:  Papers (6)  |  Patents (115)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    A new high-density DRAM cell concept is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor, generates a large bit line signal with a small cell capacitance during the read cycle. Since it does not need a large storage capacitance and one transistor is stacked on the top of the other transistor, the cell size is small and can be easily scaled down for future generations of memory devices. The unit cell size fabricated using a 4 M SRAM process without any process modification is 1.8 μm×2.85 μm. The proposed cell can be adopted to store multi-bit information. The fabricated prototype cell shows a resolution of about 3.5 bit View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-voltage low-power fully-integratable automatic gain control for hearing instruments

    Publication Year: 1994 , Page(s): 943 - 946
    Cited by:  Papers (33)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    A low-voltage low-power bipolar automatic gain control (AGC) for hearing instruments that works in the current domain and operates on a single 1.3-V battery is presented. In this AGC a large time constant (50 ms) is realized on-chip. The AGC consists of a gain cell, a comparator and a voltage follower. The active circuitry of the AGC has been integrated in the DIMES01 process and the total circuit demonstrates operation down to 1 V with only 4 μW power consumption. The compression range amounts to 38 dB. The AGC has a dynamic range (DR) of 62 dB at the output over a bandwidth of 10 kHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A multi-purpose CMOS sensor interface for low-power applications

    Publication Year: 1994 , Page(s): 952 - 956
    Cited by:  Papers (15)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    A dedicated low-power CMOS transponder microchip is presented as part of a novel telemetry implant for biomedical applications. This mixed analog-digital circuit contains an identification code and collects information on physiological parameters, i.e., body temperature and physical activity, and on the status of the battery. To minimize the amount of data to be transmitted, a dedicated signal processing algorithm is embedded within its circuitry. All telemetry functions (encoding, modulation, generation of the carrier) are implemented on the integrated circuit. Emphasis is on a high degree of flexibility towards sensor inputs and internal data management, extreme miniaturization, and low-power consumption to allow a long implantation lifetime View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3-μm gate length quantum well HEMT's

    Publication Year: 1994 , Page(s): 995 - 997
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at a bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at a supply voltage of -5 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A four-channel CMOS codec filter circuit “SICOFI-4”

    Publication Year: 1994 , Page(s): 906 - 913
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    Cost reduction by integration of complex mixed analog-digital systems on a single chip and an excellent yield to area ratio is a major goal for IC design in the nineties. In this paper, a four-channel codec-filter chip for analog subscriber lines in ISDN-orientated networks is presented, giving an exceptional example for high level system implementation combined with parallel DSP integration and analog circuitry with high performance. The chip combines four analog frontends, digital signal processing realized by different approaches for a sophisticated filter concept in addition with test strategies including digital and analog BIST. The circuit is fabricated in a standard 1-μm CMOS technology, needs a single 5-V power supply, and can easily be programmed to world-wide different country specifications and applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 5 V, 6-b, 80 Ms/s BiCMOS flash ADC

    Publication Year: 1994 , Page(s): 873 - 878
    Cited by:  Papers (13)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    A 5 V single supply, 6-bit flash A/D converter (ADC) has been developed that supports sampling rates of up to 80 Ms/s. The converter is optimized to operate in undersampling applications where the ADC has to deliver greater than 5.2 Effective Number Of Bits (ENOB's) with input frequencies well beyond Nyquist. Excellent dynamic linearity performance has been achieved with input frequencies up to 75 MHz and a gain flatness of better than 0.1 dB is obtained over the input signal spectrum of 50 MHz-95 MHz. This ADC is fabricated on a 1.0 μm advanced BiCMOS process that features trench-isolated bipolar devices with an ft of 10 GHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-speed programmable CMOS interface system combining D/A conversion and FIR filtering

    Publication Year: 1994 , Page(s): 972 - 977
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    This paper describes the design, integrated circuit realization, and experimental characterization of a high-speed programmable interface system combining the functions of digital-to-analog (D/A) conversion and FIR filtering. The system comprises four high-speed digital delay lines, with programmable delay length, together with four high-speed steering-current D/A converters with independent digitally-programmable gains. A demonstration prototype chip has been fabricated in a 1.2-μm digital CMOS technology. At 54 MHz conversion rate and digital delay lines clocked at 18 MHz, it consumes 115 mW for a full-scale output current of 13.3 mA at 5 V supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Smart-pixel cellular neural networks in analog current-mode CMOS technology

    Publication Year: 1994 , Page(s): 895 - 905
    Cited by:  Papers (33)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (868 KB)  

    This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT's connected in a Darlington structure. Pixel smartness is achieved by exploiting the cellular neural network paradigm, incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-μm technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm2, with a power consumption down to 105 μW/unit and image processing times below 2 μs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An 8-bit multitask micropower RISC core

    Publication Year: 1994 , Page(s): 986 - 991
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    This paper describes a multitask micropower RISC core. A hardware scheduler handles up to four separate tasks in a pseudo-parallel way. Task or context switching is performed at the instruction level and does not need additional instructions. In a 1.5-V low-power 2-μm technology the core area is 5-6 mm2, depending upon the global routing of the complete ASIC. Measured power consumption is 0.2 μA/kHz at 1.5 V with a low-power 8-K word ROM and a 256-byte RAM View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Programmable switched-current wave analog filters

    Publication Year: 1994 , Page(s): 927 - 935
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    This paper presents a methodology to realize programmable switched-current filters. A universal wave filter structure is built based on a low-pass (LP) to band-pass (BP) frequency transformation in the z-domain that allows obtaining different filtering functions from a single low-pass reference filter without altering the global circuit topology. Two different parameters, modified by changing the gain of current mirrors, independently control the filter bandwidth and center frequency. A 2.88-mm2 IC prototype has been fabricated in a 1.6-μm CMOS digital technology that is capable of implementing three LP's (and their three complementary HP's) and nine BP's (and their nine complementary BR) Chebyschev filters. The realization of the 24 filtering functions requires less than 15% of additional area than that required to implement only one BP function. The chip operates from a 5-V supply, dissipates 0.83 mW/pole, and met the expected performance levels for all filter functions View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System integration of optical devices and analog CMOS amplifiers

    Publication Year: 1994 , Page(s): 1006 - 1010
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    Monolithic system integration of optical components, photodetectors, and analog transimpedance CMOS amplifiers is presented. An advanced SWAMI LOCOS technique, based on a submicron CMOS process is applied. Different optical devices including waveguides, beam splitters, interferometers and mirrors have been integrated using this technique. The optical system consists of a SiON layer deposited on 2-μm oxide. The waveguides are made of structured SiO2 layers on top of the SiON layer. Leaky wave or butt coupled photodiodes and phototransistors are used as light detectors. The photocurrents are amplified by low-noise CMOS transimpedance amplifiers with high sensitivity. They were designed for a large dynamic range of photocurrents together with short recovery times and low noise. Their reliability and yield were optimized with new CAD tools View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Precise analog synapse for Kohonen feature maps

    Publication Year: 1994 , Page(s): 982 - 985
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    A plastic medium-term analog synapse is presented that fulfils the stringent specifications necessary for the Kohonen algorithm. The principle is based on a switched capacitor-like technique implementing a variable time-constant integrator. The memory leakage standard deviation is 2 mV/s for a voltage range of 2 V at room temperature and the learning gain can be varied over two decades. Its differential structure leads to good CMRR, PSRR, and charge injection cancellation. The total synapse area is &frac116; mm2 using a 3-μm self-aligned contact single-metal CMOS technology. Measurement results of a test chip are also presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-noise CMOS preamplifier operating at 4.2 K

    Publication Year: 1994 , Page(s): 921 - 926
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    A low-noise CMOS readout preamplifier operating at liquid helium temperatures is described, In conjunction with magnetic field sensors applying SQUIDs (superconducting quantum interference devices) the preamplifier can be used to measure biomagnetic fields of human brain and heart noninvasively. The input of the folded cascode amplifier can be attached directly to a low impedance SQUID output. This way the commonly used discrete LC tank resonator circuit for impedance matching can be omitted. An equivalent noise voltage density of 0.3 nV/√Hz at 500 kHz has been measured. Despite the occurrence of the kink effect and other abnormalities in MOS transistor characteristics at 4.2 K, during the tests no abnormal operation has been observed. Such a preamplifier circuit is essential in simplifying the expensive shielding currently used in biomagnetic diagnosis systems View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CMOS magnetic-field sensor system

    Publication Year: 1994 , Page(s): 1002 - 1005
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    A magnetic-field sensor system integrated in CMOS technology with additional processing steps necessary for sensor fabrication is presented. The system contains a magnetoresistive permalloy microbridge acting as a sensor, temperature compensation circuitry, programmable readout electronics, reference voltage bias, and clock generation. It features maximum magnetic flux sensitivity of 70 mV/μT (corresponds to the magnetic-field sensitivity of 88.2 mV/(A/m) at μr=1) and its temperature gain is below 260 ppm/°C in the range between -50°C and +100°C View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A programmable multi-channel CMOS pulser chip to drive ultrasonic array transducers

    Publication Year: 1994 , Page(s): 992 - 994
    Cited by:  Papers (3)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    This paper describes the development of a 16-channel programmable pulse generator Application Specific Integrated Circuit (ASIC). The General Purpose Pulser Chip (GPPC-16) can supply pulses delayed by up to 0.5 ms with a 1 ns time resolution. By employing novel design techniques, this has been achieved in standard CMOS technology. The design employs a CMOS delay line in conjunction with a phase-locked-loop. In this way a 16-phase clock is generated, which can drive 16 programmable counters. Currently the chip is being used to drive ultrasonic transducer arrays. The construction of these piezoelectric polymer arrays is also briefly discussed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan