IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 1 • Jan. 2016

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  • Table of contents

    Publication Year: 2016, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2016, Page(s): C2
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  • Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives

    Publication Year: 2016, Page(s):1 - 22
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3141 KB) | HTML iconHTML

    As CMOS technology begins to face significant scaling challenges, considerable research efforts are being directed to investigate alternative device technologies that can serve as a replacement for CMOS. Spintronic devices, which utilize the spin of electrons as the state variable for computation, have recently emerged as one of the leading candidates for post-CMOS technology. Recent experiments h... View full abstract»

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  • Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits

    Publication Year: 2016, Page(s):23 - 36
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3145 KB) | HTML iconHTML

    Efficiently optimizing large-scale, complex analog systems requires to know the performance tradeoffs for various analog circuit blocks. In this paper, we propose a radically new approach for analog performance tradeoff modeling. Our key idea is to broadly search the rich design knowledge from the Internet, and then mathematically encode the knowledge as high-dimensional performance tradeoff curve... View full abstract»

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  • SeMIA: Self-Similarity-Based IC Integrity Analysis

    Publication Year: 2016, Page(s):37 - 48
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1774 KB) | HTML iconHTML

    Counterfeit chips in the supply chain as well as hardware Trojan (HT) attacks pose serious threats to the semiconductor industry. If undetected before deployment, they can lead to serious consequences including system performance/reliability issues during field operation and potential revenue/reputation loss for a trusted manufacturer. Currently, no unified detection method is available that can s... View full abstract»

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  • On Reverse Engineering-Based Hardware Trojan Detection

    Publication Year: 2016, Page(s):49 - 57
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1080 KB) | HTML iconHTML

    Due to design and fabrication outsourcing to foundries, the problem of malicious modifications to integrated circuits (ICs), also known as hardware Trojans (HTs), has attracted attention in academia as well as industry. To reduce the risks associated with Trojans, researchers have proposed different approaches to detect them. Among these approaches, test-time detection approaches have drawn the gr... View full abstract»

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  • Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems

    Publication Year: 2016, Page(s):58 - 71
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2255 KB) | HTML iconHTML

    NAND flash memory has been widely deployed in embedded systems, personal computers, and data centers. While recent technology scaling and density improvement have reduced its price, they have also significantly shortened its endurance. In this paper, with the understanding of the relationship between data retention time and flash wearing, a retention trimming approach, which trims data retention t... View full abstract»

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  • Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs

    Publication Year: 2016, Page(s):72 - 85
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2330 KB) | HTML iconHTML

    There have been several efforts on run-time mapping of applications on multiprocessor-systems-on-chip. These traditional efforts perform either on-the-fly processing or use design-time analyzed results. However, on-the-fly processing often leads to low-quality mappings, and design-time analysis becomes computationally costly for large-size problems and require huge storage for large number of appl... View full abstract»

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  • QMDDs: Efficient Quantum Function Representation and Manipulation

    Publication Year: 2016, Page(s):86 - 99
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1076 KB) | HTML iconHTML

    Quantum mechanical phenomena such as phase shifts, superposition, and entanglement show promise in use for computation. Suitable technologies for the modeling and design of quantum computers and other information processing techniques that exploit quantum mechanical principles are in the range of vision. Quantum algorithms that significantly speed up the process of solving several important comput... View full abstract»

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  • A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

    Publication Year: 2016, Page(s):100 - 113
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2318 KB) | HTML iconHTML

    Many modern applications exhibit a dynamic and nonstationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization a... View full abstract»

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  • MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool

    Publication Year: 2016, Page(s):114 - 127
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2398 KB) | HTML iconHTML

    Transistor count minimization is an important goal as very-large-scale integration technology approaches its technical and physical limits. In this paper, we present a computer-aided design synthesis tool that tries to minimize the number of transistors required to implement a given multiple-output logic function. The proposed transistor-level synthesis approach goes beyond the traditional series-... View full abstract»

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  • Nearly-2-SAT Solutions for Segmented-Channel Routing

    Publication Year: 2016, Page(s):128 - 140
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1184 KB) | HTML iconHTML

    This paper proposes a nearly-2-satisfiability (SAT) routing solution for segmented-channels in row-based field programmable gate array architectures. Both dogleg-free routing and routing with dog-legging are considered here. The constraints for these problems have been expressed as Boolean conjunctive norm form (CNF) clauses and the conjunction of these clauses creates a Boolean function. The form... View full abstract»

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  • Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains

    Publication Year: 2016, Page(s):141 - 154
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1251 KB) | HTML iconHTML

    As the number of frequency domains aggressively grows in today's systems-on-chip (SoCs), the delivery of high-delay test quality across numerous frequency domains while meeting test budgets assumes crucial importance. This paper proposes a method to explore the delay test quality tradeoffs across these domains, determining an optimal distribution of the test time budget across all domains while mi... View full abstract»

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  • Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array

    Publication Year: 2016, Page(s):155 - 165
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2752 KB) | HTML iconHTML

    Static random access memories (SRAM) are a major constituent in high performance microprocessors and systems-on-a-chip. With scaling of technology, manufacturing process variations in SRAMs are of significant concern. SRAM cells that are marginal due to process variations suffer from stability issues where random thermal noise and random telegraph noise (RTN) become determinant in memory state. Th... View full abstract»

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  • Compact Modeling of Phase-Locked Loop Frequency Synthesizer for Transient Phase Noise and Jitter Simulation

    Publication Year: 2016, Page(s):166 - 170
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1074 KB) | HTML iconHTML

    Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is... View full abstract»

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  • Introducing IEEE Collabratec

    Publication Year: 2016, Page(s): 171
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  • IEEE Access

    Publication Year: 2016, Page(s): 172
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2016, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2016, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu