# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 45

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2015, Page(s): C2
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• ### High-Throughput Trellis Processor for Multistandard FEC Decoding

Publication Year: 2015, Page(s):2757 - 2767
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Trellis codes, including Low-Density Parity-Check (LDPC), turbo, and convolutional code (CC), are widely adopted in advanced wireless standards to offer high-throughput forward error correction (FEC). Designing a multistandard FEC decoder is of great challenge. In this paper, a trellis application specified instruction-set processor (TASIP) is presented for multistandard trellis decoding. A unifie... View full abstract»

• ### A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications

Publication Year: 2015, Page(s):2768 - 2781
Cited by:  Papers (2)
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The first single-chip design that supports real-time H.264/Advanced Video Coding decoding of 8k (7680×4320) 60 frames/s is realized. It also supports multiview decoding for up to 32720p views or 161080p views. To significantly improve the throughput and reduce the memory bandwidth requirement, frame-level parallelism is exploited for the proposed design. First, a frame dependency protection... View full abstract»

• ### Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

Publication Year: 2015, Page(s):2782 - 2790
Cited by:  Papers (6)
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Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralow-power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder... View full abstract»

• ### Cost-Efficient Frequency-Domain MIMO–OFDM Modem With an SIMD ALU-Based Architecture

Publication Year: 2015, Page(s):2791 - 2803
Cited by:  Papers (1)
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In this paper, a single instruction multiple data (SIMD) arithmetic logic unit (ALU)-based architecture is proposed to improve hardware efficiency in a 4 × 4 frequency-domain multiple input multiple output-orthogonal frequency division multiplexing modem based on a space-time block code (STBC). The majority of mathematic units in the proposed architecture are centralized so that any mathema... View full abstract»

• ### Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications

Publication Year: 2015, Page(s):2804 - 2812
Cited by:  Papers (10)
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Efficient cryptographic architectures are used extensively in sensitive smart infrastructures. Among these architectures are those based on stream ciphers for protection against eavesdropping, especially when these smart and sensitive applications provide life-saving or vital mechanisms. Nevertheless, natural defects call for protection through design for fault detection and reliability. In this p... View full abstract»

• ### A 0.13- $\mu$ m CMOS Current-Mode All-Pass Filter for Multi-GHz Operation

Publication Year: 2015, Page(s):2813 - 2818
Cited by:  Papers (4)
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A CMOS wide-bandwidth first-order current-mode all-pass filter (APF) is discussed. The circuit consists of one transistor, a resistor, a grounded inductor, and a load. When used with a current mirror as the load, the current-mode filter exhibits a high output impedance, which is advantageous from an integration point of view and enables this configuration to be cascaded with current-mode circuits.... View full abstract»

• ### A 2-GHz Bandwidth, Integrated Transimpedance Amplifier for Single-Photon Timing Applications

Publication Year: 2015, Page(s):2819 - 2828
Cited by:  Papers (2)
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In recent years, single-photon timing techniques have been employed in a steadily increasing number of applications. Most of these applications require high detector performance in terms of noise, photon detection efficiency, time resolution, and number of pixels operating in parallel. The detectors best fitting these requirements are single-photon avalanche diode (SPAD) arrays built in custom tec... View full abstract»

• ### A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s Advanced Techniques-Based Novel Intrabody Communication Receiver Analog Front End

Publication Year: 2015, Page(s):2829 - 2841
Cited by:  Papers (4)
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This paper presents a low power, long-transmission distance, high data rate intrabody communication (IBC) analog receiver front end (RFE). First, to optimize the transmission performance, conventional transmission line analysis scheme is creatively adopted to the IBC design to characterize the body channel. Second, switched-capacitor filters based on sampling rate boosting technique are adopted fo... View full abstract»

• ### Searching for Spectrum Holes: A 400–800 MHz Spectrum Sensing System

Publication Year: 2015, Page(s):2842 - 2851
Cited by:  Papers (3)
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A 400-800 MHz spectrum sensing system is designed and implemented using 0.18-μm CMOS technology for cognitive radios in the UHF TV band. Based on envelope detection, the system employs a down converter, a digitally controlled oscillator, a low-pass filter (LPF), a rectifier, a comparator, and a digital control unit to realize spectrum sensing with 10-bit frequency representation. With varia... View full abstract»

• ### Delay-Lock-Loop-Based Inductorless and Electrolytic Capacitorless Pseudo-Sine-Current Controller in LED Lighting Systems

Publication Year: 2015, Page(s):2852 - 2861
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Light-emitting diode lighting system with the proposed pseudo-sine-current controller removes most of the external passive components, which include inductor, electrolytic capacitor, freewheel diode, blocking diode, and the bleeding circuit for Triac dimming control, for low cost and small volume. Delay-lock loop control can ensure the in-phase operation of ac input voltage and current for high po... View full abstract»

• ### Synthesis for Width Minimization in the Single-Electron Transistor Array

Publication Year: 2015, Page(s):2862 - 2875
Cited by:  Papers (3)
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Power consumption has become one of the primary challenges to meetMoore's law. For reducing power consumption, single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow power consumption in operation. Previous works have proposed automated mapping approaches for SET arrays that focused on minimizing the number of ... View full abstract»

• ### Run-Time Management for Multicore Embedded Systems With Energy Harvesting

Publication Year: 2015, Page(s):2876 - 2889
Cited by:  Papers (2)
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In this paper, we propose a novel framework for runtime energy and workload management in multicore embedded systems with solar energy harvesting and a periodic hard real-time task set as the workload. Compared with prior work, our framework makes several novel contributions and possesses several advantages, including the following: 1) a semidynamic scheduling heuristic that dynamically adapts to ... View full abstract»

• ### Efficient and Correct by Construction Assertion-Based Synthesis

Publication Year: 2015, Page(s):2890 - 2901
Cited by:  Papers (2)
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We propose a unifying formalization of the concepts of monitor and reactant, and derive a modular synthesis method to achieve automatic generation of compliant modules from declarative temporal specifications. The founding dependence relation and its hardware interpretation provide an algorithm to automatically decide which signals are observed and which are generated. The method is efficient, and... View full abstract»

• ### Bayesian Prediction-Based Energy-Saving Algorithm for Embedded Intelligent Terminal

Publication Year: 2015, Page(s):2902 - 2912
Cited by:  Papers (4)
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The Internet of Things (IoT) has received an increasing attention in recent years. Embedded intelligent terminal (EIT), an indispensable part of IoT, works not only as a sensor but also as a primary processor. Due to the limited power resource of EIT, it is important to study how to improve the efficiency of its power use. To tackle this problem, we propose an energy-saving algorithm, Bayesian idl... View full abstract»

• ### VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm

Publication Year: 2015, Page(s):2913 - 2921
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Increasing demand of high-speed portable modules for multimedia applications has motivated the development of hardware-based solutions for image processing applications. Most of the nonrigid image registration algorithms are found to be unsuitable for hardware implementation because of their nonlinearity and computationally intensive nature. In this paper, an algorithm for nonrigid image registrat... View full abstract»

• ### Noise Modeling and Analysis of SAR ADCs

Publication Year: 2015, Page(s):2922 - 2930
Cited by:  Papers (11)
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A generic statistical model for calculating input-referred noise of an analog-to-digital converter (ADC) impaired by thermal noise is proposed. Based on this model, detailed statistical analyses are performed on three successive approximation register (SAR) ADCs and the analytical results obtained are verified with Monte Carlo simulations. To compare the input-referred noise of different SAR ADC a... View full abstract»

• ### Coupling Mitigation in 3-D Multiple-Stacked Devices

Publication Year: 2015, Page(s):2931 - 2944
Cited by:  Papers (5)
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A 3-D multiple-stacked IC has been proposed to support energy efficiency for data center operations as dynamic RAM (DRAM) scaling improves annually. 3-D multiple-stacked IC is a single package containing multiple dies, stacked together, using through-silicon via (TSV) technology. Despite the advantages of 3-D design, fault occurrence rate increases with feature-size reduction of logic devices, whi... View full abstract»

• ### Figures-of-Merit to Evaluate the Significance of Switching Noise in Analog Circuits

Publication Year: 2015, Page(s):2945 - 2956
Cited by:  Papers (5)
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An analysis flow is proposed to determine the significance of induced (switching) noise in analog circuits. The proposed flow is exemplified through two commonly used amplifier topologies. Specifically, input-referred switching noise is introduced as the first figure-of-merit and compared with the well-known equivalent input device noise through analytic expressions. The comparison is achieved as ... View full abstract»

• ### Variability in Multistage Synchronizers

Publication Year: 2015, Page(s):2957 - 2969
Cited by:  Papers (2)
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System-on-a-chip designs typically employ multiple clock domains to interface several externally clocked circuits operating at different frequencies and to reduce power and area by breaking large clock trees into multiple small ones. The principal challenge of such globally asynchronous locally synchronous architectures is the need to reliably communicate between the different clock domains. To ac... View full abstract»

• ### Design and Implementation of Time and Frequency Synchronization in LTE

Publication Year: 2015, Page(s):2970 - 2982
Cited by:  Papers (6)
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A novel architecture for efficient time and frequency synchronization, applied to the long-term evolution (LTE) standard, is proposed. For symbol timing, we propose applying a symbol-folding method on top of the sign-bit reduction technique, leading to a novel algorithm for the cyclic prefix-type recognition in LTE. Following the symbol timing, the fractional carrier frequency offset is estimated ... View full abstract»

• ### Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power Gating

Publication Year: 2015, Page(s):2983 - 2991
Cited by:  Papers (2)
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In traditional decoupling capacitor topologies, power gating can significantly degrade the system-wide power integrity of a 3-D integrated circuit since the decoupling capacitance associated with the power-gated block/plane becomes ineffective for the neighboring, active planes. Two topologies are investigated to alleviate this issue by exploiting: 1) relatively low-resistance through silicon vias... View full abstract»

• ### Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs

Publication Year: 2015, Page(s):2992 - 3005
Cited by:  Papers (2)
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Large temperature gradients exacerbate various types of defects including early-life failures and delay faults. Efficient detection of these defects requires that burn-in and test for delay faults, respectively, are performed when temperature gradients with proper magnitudes are enforced on an Integrated Circuit (IC). This issue is much more important for 3-D stacked ICs (3-D SICs) compared with 2... View full abstract»

• ### Test Compaction by Sharing of Functional Test Sequences Among Logic Blocks

Publication Year: 2015, Page(s):3006 - 3014
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This paper describes a test compaction procedure that considers a set of functional test sequences for a set of logic blocks in a design. The logic blocks may have different numbers of primary inputs, and functional test sequences of different lengths. The procedure expands the test sequences such that every sequence is applicable to every logic block. It then concatenates and compacts the sequenc... View full abstract»

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu