IEEE Transactions on Electron Devices

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Publication Year: 2015, Page(s):C1 - 3903
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• IEEE Transactions on Electron Devices publication information

Publication Year: 2015, Page(s): C2
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• Change of Editor-in-Chief

Publication Year: 2015, Page(s): 3904
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• Kudos To Our Reviewers

Publication Year: 2015, Page(s): 3905
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• Golden List of Reviewers for 2015

Publication Year: 2015, Page(s):3906 - 3937
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• Adapting Interconnect Technology to Multigate Transistors for Optimum Performance

Publication Year: 2015, Page(s):3938 - 3944
Cited by:  Papers (5)
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Beyond the 22-nm technology node, interconnect parasitics are increasingly contributing to the degradation of circuit performance. Thus, the focus is on optimizing interconnect parasitics in order to achieve optimum performance. The increased total device capacitance and the reduced device resistance of multigate transistors amplify the importance of wire resistance in circuit delay. In this paper... View full abstract»

• FinFET Evolution Toward Stacked-Nanowire FET for CMOS Technology Scaling

Publication Year: 2015, Page(s):3945 - 3950
Cited by:  Papers (8)  |  Patents (1)
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The performance of an evolutionary FinFET design (iFinFET) is benchmarked against that of the conventional bulk FinFET and stacked-nanowire gate-all-around (GAA) FET, through3-D device simulations, for both n-channel and p-channel transistors. The results show that the iFinFET provides for improved electrostatic integrity relative to the FinFET, but with substantially less gate capacitance penalty... View full abstract»

• Comparison of Gate-Metal Work Function Variability Between Ge and Si p-Channel FinFETs

Publication Year: 2015, Page(s):3951 - 3956
Cited by:  Papers (3)
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In this paper, for the first time, the performance of a Ge p-channel FinFET in the presence of random grain-orientation-induced gate-metal work function variability (WFV) is reported. The statistical fluctuation in threshold voltage (VT) and subthreshold swing (SS) are estimated for a Ge p-FinFET of varying channel length, fin width, equivalent oxide thickness of the gate dielectric, and supply vo... View full abstract»

• Analysis and Equivalent-Circuit Model for CMOS On-Chip Multiple Coupled Inductors in the Millimeter-Wave Region

Publication Year: 2015, Page(s):3957 - 3964
Cited by:  Papers (8)
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A growing number of on-chip inductors have been applied in the millimeter-wave IC design. The coupling effects between them have a negative impact on the performance of the circuit and each on-chip inductor. In this paper, a new equivalent-circuit model and a parameter extraction method for multiple on-chip inductors in the millimeter-wave region are proposed. The impacts of coupling effects on ev... View full abstract»

• Nanoscale-RingFET: An Analytical Drain Current Model Including SCEs

Publication Year: 2015, Page(s):3965 - 3972
Cited by:  Papers (4)
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In this paper, using a 2-D Poisson equation (in cylindrical coordinates), an analytical drain current model of a nanoscale RingFET architecture has been developed for the first time. Major short-channel effects, such as channel length modulation, velocity scattering, and drain-induced barrier lowering, are taken under consideration while developing the model. A bandgap narrowing model has been emp... View full abstract»

• Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain

Publication Year: 2015, Page(s):3973 - 3979
Cited by:  Papers (22)
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In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs). We propose a mixed TFET-MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power co... View full abstract»

• Electrical Behavior of MBE Grown Interfacial Misfit GaSb/GaAs Heterostructures With and Without Te-Doped Interfaces

Publication Year: 2015, Page(s):3980 - 3986
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A detailed study of interface states in interfacial misfit (IMF) grown GaSb on GaAs substrates is presented. Two types of structures, namely, uncompensated and Te compensated, are investigated using current-voltage, capacitance-frequency, conductance-frequency, and deep level transient spectroscopy techniques. Our studies reveal that incorporation of Te at the interface (IMF) causes a degradation ... View full abstract»

• Impact of AlN Interfacial Dipole on Effective Work Function of Ni and Band Alignment of Ni/HfO2/In0.53Ga0.47As Gate-Stack

Publication Year: 2015, Page(s):3987 - 3991
Cited by:  Papers (9)
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AlN has successfully been applied to passivate the oxide/III-V interface; however, it changes both the metal work function (WF) and band alignment of the gate-stack and, thus, affects the power consumption of the devices. We found that the AlN layer induces a dipole δ = 0.18 eV between HfO2 and substrate. The dipole value obtained from capacitance- voltage characteristics perform... View full abstract»

• Thermal Characterization Using Optical Methods of AlGaN/GaN HEMTs on SiC Substrate in RF Operating Conditions

Publication Year: 2015, Page(s):3992 - 3998
Cited by:  Papers (7)
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Performance and reliability of wide bandgap high-power amplifiers are correlated with their thermal behavior. Thermal model development and suitable temperature measurement systems are necessary to quantify the channel temperature of devices in real operating conditions. As a direct temperature measurement within a channel is most of the time not achievable, the common approach is to measure the d... View full abstract»

• Transparent JFETs Based on $p$ -NiO/ $n$ -ZnO Heterojunctions

Publication Year: 2015, Page(s):3999 - 4003
Cited by:  Papers (4)
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The fabrication of all-oxide junction-FETs consisting of n-type ZnO channels and p-type NiO gate electrodes with high optical transmission in the visible spectral range is reported. The influence of the channel layer thickness on the transfer characteristics in terms of ON-voltage, current ON/OFF ratio, and subthreshold slope was investigated. Best devices showed channel mobilities of around 4 cm<... View full abstract»

• All-Oxide Inverters Based on ZnO Channel JFETs With Amorphous ZnCo2O4 Gates

Publication Year: 2015, Page(s):4004 - 4008
Cited by:  Papers (5)
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We present integrated inverter circuits based on junction FETs (JFETs) with ZnO channels and amorphous ZnCo2O4 gate contacts. The inverters reach high gain values up to 276 and uncertainty ranges down to 0.3 V for an operating voltage of 3 V. The magnitude of the gain is traced back theoretically to the slope of the JFET saturation current. The use of a level shifter is demonstrated, in order to o... View full abstract»

• Nonvolatile Programmable Switch With Adjacently Integrated Flash Memory and CMOS Logic for Low-Power and High-Speed FPGA

Publication Year: 2015, Page(s):4009 - 4014
Cited by:  Papers (3)
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Novel nonvolatile programmable switch for low-power and high-speed field-programmable gate array (FPGA) where flash memory is adjacently integrated to CMOS logic is demonstrated. The flash memory and the high-speed switching transistor (SwTr) are fabricated close to each other without deteriorating their respective performance. Furthermore, programming schemes to write and erase the flash memory a... View full abstract»

• Programming Current Reduction via Enhanced Asymmetry-Induced Thermoelectric Effects in Vertical Nanopillar Phase-Change Memory Cells

Publication Year: 2015, Page(s):4015 - 4021
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Thermoelectric effects are envisioned to reduce programming currents in nanopillar phase-change memory (PCM) cells. However, due to the inherent symmetry in such a structure, the contribution due to thermoelectric effects on programming currents is minimal. In this paper, we propose a hybrid PCM structure, which incorporates a twofold asymmetry specifically aimed to favorably enhance the thermoele... View full abstract»

• Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design

Publication Year: 2015, Page(s):4022 - 4028
Cited by:  Papers (29)
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In this paper, we present a compact model for metal-oxide-based resistive random access memory (RRAM) devices with bipolar switching characteristics. The switching mechanism relies on the dynamics of conductive filament growth/dissolution in the oxide layer. Besides the dc and pulsed I-V characteristics, the model also captures the RRAM retention property and the temperature dynamics. The model pa... View full abstract»

• On the Origin of Low-Resistance State Retention Failure in HfO2-Based RRAM and Impact of Doping/Alloying

Publication Year: 2015, Page(s):4029 - 4036
Cited by:  Papers (16)
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We study in detail the impact of alloying HfO2 with Al (Hf1_xAl2xO2+x) on the oxide-based resistive random access memory (RRAM) (OxRRAM) thermal stability through material characterization, electrical measurements, and atomistic simulation. Indeed, migration of oxygen atoms inside the dielectric is at the heart of OxRRAM operations. Hence, we performed c... View full abstract»

• Threshold Voltage Shift Effect of a-Si:H TFTs Under Bipolar Pulse Bias

Publication Year: 2015, Page(s):4037 - 4043
Cited by:  Papers (2)
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Threshold voltage shift (ΔVTH) effect of hydrogenated amorphous silicon thin-film transistors under bipolar pulse bias stress (BPBS) is investigated. The dependence of the ΔVTH effect on the signal pulsewidth, stress temperature, and negative pulse voltage magnitude of the BPBS is systematically measured, and explained by the charge trapping and detrapping theor... View full abstract»

• Integrated a-Si:H Gate Driver With Low-Level Holding TFTs Biased Under Bipolar Pulses

Publication Year: 2015, Page(s):4044 - 4050
Cited by:  Papers (3)
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A hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver on array with low-level holding TFTs (LLH TFTs) biased under bipolar pulse is investigated. It is shown that the bipolar bias at low frequency significantly alleviates the threshold voltage shift of the LLH TFTs. As a result, the lifetime of the proposed gate driver is demonstrated to be several times of that under th... View full abstract»

• Benchmarking of MoS2 FETs With Multigate Si-FET Options for 5 nm and Beyond

Publication Year: 2015, Page(s):4051 - 4056
Cited by:  Papers (6)
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In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but als... View full abstract»

• Suppression of Light Influx Into the Channel Region of Photosensitive Thin-Film Transistors

Publication Year: 2015, Page(s):4057 - 4062
Cited by:  Papers (1)
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Analysis on the light influx into a bottom-gate, etch-stopper structure thin-film transistor is presented. Reduction of the light influx by means of structural changes in the device can lead to a universal improvement in negative-bias temperature illumination stress instability of metal-oxide transistors. When the devices are illuminated by a fixed light source from below, the dominant light influ... View full abstract»

• Electrical Characterization of Flexible InGaZnO Transistors and 8-b Transponder Chip Down to a Bending Radius of 2 mm

Publication Year: 2015, Page(s):4063 - 4068
Cited by:  Papers (17)
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In this paper, we present the fabrication and characterization of highly flexible indium-gallium-zinc-oxide (IGZO)-based thin-film transistors (TFTs) and integrated circuits on a transparent and thin polymer substrate. Mechanical reliability tests are performed under bending conditions down to a bending radius of 2 mm. All the TFT parameters show only a weak dependence on mechanical strain. TFTs c... View full abstract»

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

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Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy