# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 48

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2015, Page(s): C2
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• ### Incoherent Undersampling-Based Waveform Reconstruction Using a Time-Domain Zero-Crossing Metric

Publication Year: 2015, Page(s):2357 - 2370
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Incoherent undersampling-based waveform acquisition provides a low-cost test setup for characterizing high-speed systems. A periodic waveform reconstruction using incoherent undersampling remaps time indices of samples using the modulus of the suspected period of the signal, effectively folding the signal into a time window equal to one period. The major cost and accuracy limitations of the recons... View full abstract»

• ### A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter

Publication Year: 2015, Page(s):2371 - 2383
Cited by:  Papers (2)
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This paper presents a 6-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog converter (RASD). By applying the input folding technique in the input stage and utilizing the flash-assisted TI-SAR ADC with the proposed RASD, the static power dissipation is reduced by 69%. ON-chip and OFF-chip ... View full abstract»

• ### Comparator Power Reduction in Low-Frequency SAR ADC Using Optimized Vote Allocation

Publication Year: 2015, Page(s):2384 - 2394
Cited by:  Papers (4)
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When operating at scaled supply voltages, the primary source of performance degradation in a successive approximation register (SAR) analog-to-digital converter (ADC) is the comparator thermal noise. Low-noise comparator can be used but at the expense of increased power dissipation. This paper presents an approach to reduce the comparator power in SAR ADCs. A mathematical model of a SAR ADC derive... View full abstract»

• ### A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters

Publication Year: 2015, Page(s):2395 - 2407
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This paper presents a highly digital calibration technique suitable for high-speed digital-to-analog converters (DACs). The proposed calibration method does not require an adjustment of on-chip analog voltages and can therefore be a favorable method in a deeply scaled nanometer process. The calibration utilizes that adding several redundant unit current cells to predetermined weight groups can be ... View full abstract»

• ### An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications

Publication Year: 2015, Page(s):2408 - 2416
Cited by:  Papers (2)
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Many image/video processing algorithms require FIFO for filtering. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. We have proposed an energy- and area-efficient FIFO design for image/video applications through FIFO with error-reduced data compression (FERDC) and near-threshold operation. On architecture level, FERDC techni... View full abstract»

• ### Temperature-Centric Reliability Analysis and Optimization of Electronic Systems Under Process Variation

Publication Year: 2015, Page(s):2417 - 2430
Cited by:  Papers (1)
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Electronic system designs that ignore process variation are unreliable and inefficient. In this paper, we propose a system-level framework for the analysis of temperature-induced failures that considers the uncertainty due to process variation. As an intermediate step, we also develop a probabilistic technique for dynamic steady-state temperature analysis. Given an electronic system under a certai... View full abstract»

• ### Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs

Publication Year: 2015, Page(s):2431 - 2437
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This paper proposes a novel voltage scaling low-power design methodology for large system-on-chip (SoC) designs. It scales the supply voltage to a SoC based on operating conditions and bit error rate in a system. It allows occasional timing errors in the circuit and relies on a forward error correction that already exists in the system to correct the errors. As a result, the proposed technique imp... View full abstract»

• ### A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations

Publication Year: 2015, Page(s):2438 - 2446
Cited by:  Papers (6)
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In this paper, we present a new 9T SRAM cell that has good write ability and improves read stability at the same time. Simulation results show that the proposed design increases read static noise margin and ION/IOFF of read path by 219% and 113%, respectively, at supply voltage of 300-mV over conventional 6T SRAM cell in a 90-nm CMOS technology. The proposed design lets us reduce the minimum opera... View full abstract»

• ### Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving

Publication Year: 2015, Page(s):2447 - 2460
Cited by:  Papers (2)
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We propose a technology-independent vulnerability-driven parity selection method for protecting modern microprocessor in-core memory arrays against multiple-bit upsets (MBUs). As MBUs constitute over 50% of the upsets in recent technologies, error correcting codes or physical interleaving are typically employed to effectively protect out-of-core memory structures, such as caches. Such methods, how... View full abstract»

• ### A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance

Publication Year: 2015, Page(s):2461 - 2472
Cited by:  Papers (1)
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Synchronizers play a key role in multiclock domains systems on chip and their performance is usually measured by the mean-time between failures (MTBF) of the system. Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling for library flip-flop circuits in 65 nm and below. This degradation of parameters becomes critical when the system is operated under e... View full abstract»

• ### A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems

Publication Year: 2015, Page(s):2473 - 2486
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The snoopy-based protocol is a widely used cache coherence mechanism for a symmetric multiprocessor (SMP) system. However, this broadcast-based protocol blindly disseminates data sharing information across the system, and introduces many unnecessary data operations. This paper proposes a novel architecture of double-layer counting Bloom filter (DLCBF) to reduce the unnecessary data lookups on the ... View full abstract»

• ### A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector

Publication Year: 2015, Page(s):2487 - 2496
Cited by:  Papers (1)
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A system clock with a 50% duty cycle is demanded in high-speed data communication applications, such as double data rate memories and double sampling analog-to-digital converters. In this paper, a wide-range low-cost all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC uses a delay-recycled half-cycle time delay line to reduce the required length of the delay line to half of t... View full abstract»

• ### Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units

Publication Year: 2015, Page(s):2497 - 2507
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This paper presents the implementation of a speaker-verification system on field programmable gate array. The algorithm is executed by software over an embedded system that includes a MicroBlaze microprocessor connected to a vector floating-point unit (VFPU). The VFPU is designed to speed up the resolution of any vector floating-point operation involved in the verification algorithm, whereas the m... View full abstract»

• ### An Efficient List Decoder Architecture for Polar Codes

Publication Year: 2015, Page(s):2508 - 2518
Cited by:  Papers (15)
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Long polar codes can achieve the symmetric capacity of arbitrary binary-input discrete memoryless channels under a low-complexity successive cancelation (SC) decoding algorithm. However, for polar codes with short and moderate code lengths, the decoding performance of the SC algorithm is inferior. The cyclic-redundancy-check (CRC)-aided SC-list (SCL)-decoding algorithm has better error performance... View full abstract»

• ### ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design

Publication Year: 2015, Page(s):2519 - 2530
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This paper presents a topology-based solution for a low-skew rotary oscillator array (ROA) clock distribution network design. An ROA-brick structure is proposed that limits the traveling wave oscillation to only two uniform ring rotation directions in the ROA-brick: all the rings in clockwise (CW) direction or all the rings in counter CW direction. An ROA built from the ROA-bricks has the followin... View full abstract»

• ### Stream Processor for Real-Time Inverse Tone Mapping of Full-HD Images

Publication Year: 2015, Page(s):2531 - 2539
Cited by:  Papers (1)
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In this paper, an architecture design of a hardware accelerator capable to expand the dynamic range of low dynamic range images to the 32-bit high dynamic range counterpart is presented. The processor implements on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, to elaborate a full-HD (1920 $\times$ 1080 pixels) image in 16.6 ms (60 frames/s) on field-progra... View full abstract»

• ### CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning

Publication Year: 2015, Page(s):2540 - 2551
Cited by:  Papers (3)
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Designing low noise-to-signal-ratio (NSR) structures is one of the main concerns when implementing hardware-based neural networks. In this paper, a new continuous valued number system (CVNS) multiplication algorithm for low-resolution environment is proposed with accurate results. Using the proposed CVNS multiplication algorithm, VLSI implementation of a high-resolution mixed-signal CVNS synapse m... View full abstract»

• ### Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison

Publication Year: 2015, Page(s):2552 - 2565
Cited by:  Papers (9)
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Optical networks-on-chip (ONoCs) using wavelength-division multiplexing (WDM) technology have progressively attracted more and more attention for their use in tackling the high-power consumption and low bandwidth issues in growing metallic interconnection networks in multiprocessor systems-on-chip. However, the basic optical devices employed to construct WDM-based ONoCs are imperfect and suffer fr... View full abstract»

• ### A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures

Publication Year: 2015, Page(s):2566 - 2580
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This paper proposes a flexible energy- and reliability-aware application mapping approach for network-on-chip (NoC)-based reconfigurable architecture. A parameterized cost model is first developed by combining energy and reliability with a weight parameter that defines the optimization priority. Using this model, the overall mapping cost could be evaluated. Subsequently, a mapping method using bra... View full abstract»

• ### Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures

Publication Year: 2015, Page(s):2581 - 2594
Cited by:  Papers (1)
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Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their flexibility and efficiency. Loops in applications are often mapped onto CGRAs for acceleration, and the mapping of loops onto CGRA is quite a challenging work due to the parallel execution paradigm and constrained hardware resource. To map loops onto CGRAs efficiently, it is important to transform loop... View full abstract»

• ### Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework

Publication Year: 2015, Page(s):2595 - 2605
Cited by:  Papers (1)
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Optimization-simulation loop-based method is popular and efficient in design migration/reuse automation. However, it is only restricted to be used in block-level due to the complexity of current mixed-signal system. This paper presents a hierarchical methodology for efficiently migrating mixed-signal circuit design from one technology node to another, while keeping the same circuit and layout topo... View full abstract»

• ### Deterministic Random Walk: A New Preconditioner for Power Grid Analysis

Publication Year: 2015, Page(s):2606 - 2616
Cited by:  Papers (1)
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Iterative linear equation solvers rely on high-quality preconditioners to achieve fast convergence. For sparse symmetric systems arising from large power grid analysis problems, however, preconditioners generated by traditional incomplete Cholesky factorization are usually of low quality, resulting in slow convergence. On the other hand, preconditioners generated by random walks are quite effectiv... View full abstract»

• ### A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification

Publication Year: 2015, Page(s):2617 - 2628
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Vectorless power grid verification is a practical approach for early stage safety check without input current patterns. The power grid is usually formulated as a linear system and requires intensive matrix inversion and numerous linear programming (LP), which is extremely time-consuming for large-scale power grid verification. In this paper, the power grid is represented in the manner of domain-de... View full abstract»

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu