# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 75
• ### Front cover

Publication Year: 2015, Page(s): C1
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2015, Page(s): C2
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Publication Year: 2015, Page(s):3453 - 3456
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• ### Foreword Special Section on the 60th Anniversary of the International Electron Device Meeting

Publication Year: 2015, Page(s):3457 - 3458
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For over 60 years, the International Electron Device Meeting (IEDM) has been the world’s forum for reporting innovation, discovery, and breakthroughs in electron device technology. The IEDM, being the Electron Device Society’s flagship conference, stands out for its outstanding technical program covering the latest advances in the design, modeling, physics, characterization, and manu... View full abstract»

• ### 2D Semiconductor FETs—Projections and Design for Sub-10 nm VLSI

Publication Year: 2015, Page(s):3459 - 3469
Cited by:  Papers (33)
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Two-dimensional (2D) crystal semiconductors, such as the well-known molybdenum disulfide (MoS2), are witnessing an explosion in research activities due to their apparent potential for various electronic and optoelectronic applications. In this paper, dissipative quantum transport simulations using nonequilibrium Green's function formalism are performed to rigorously evaluate the scalabi... View full abstract»

• ### Impact of Intrinsic Channel Scaling on InGaAs Quantum-Well MOSFETs

Publication Year: 2015, Page(s):3470 - 3476
Cited by:  Papers (13)
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Using a novel gate-last process scheme that affords precise channel thickness control, we have fabricated self-aligned InGaAs quantum-well (QW) MOSFETs. Devices with a channel thickness between 3 and 12 nm, and a gate length between 40 nm and 5 μm are fabricated on a heterostructure that includes a composite InGaAs/InAs QW and an InP barrier. It is observed that channel thickness has a stro... View full abstract»

• ### Cross-Point Resistive RAM Based on Field-Assisted Superlinear Threshold Selector

Publication Year: 2015, Page(s):3477 - 3481
Cited by:  Papers (19)
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We report a 3-D-stackable 1S1R passive cross-point resistive random access memory (RRAM). The sneak (leakage) current challenge in the cross-point RRAM integration has been overcome utilizing a field-assisted superlinear threshold selector. The selector offers high selectivity of >107, sharp switching slope of <;5 mV/decade, ability to tune the threshold voltage, stable operation ... View full abstract»

• ### Investigation of Forming, SET, and Data Retention of Conductive-Bridge Random-Access Memory for Stack Optimization

Publication Year: 2015, Page(s):3482 - 3489
Cited by:  Papers (4)
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In this paper, we investigate in depth Forming, SET, and Retention of conductive-bridge random-access memory (CBRAM). A kinetic Monte Carlo model of the CBRAM has been developed considering ionic hopping and chemical reaction dynamics. Based on inputs from ab initio calculations and the physical properties of the materials, the model offers the simulation of both the Forming/SET and the Data Reten... View full abstract»

• ### Cell Variability Impact on the One-Selector One-Resistor Cross-Point Array Performance

Publication Year: 2015, Page(s):3490 - 3497
Cited by:  Papers (4)
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This paper investigates the impact of cell variability on the read performance of the one-selector one-resistor (1S1R) cross-point array. A variability-aware array-sizing analysis methodology is introduced, considering three independent variability sources, namely, the data pattern randomness, the selector variability, and the resistive switching element (RSE) variability. By analyzing the impact ... View full abstract»

• ### Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element

Publication Year: 2015, Page(s):3498 - 3507
Cited by:  Papers (59)
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Using two phase-change memory devices per synapse, a three-layer perceptron network with 164 885 synapses is trained on a subset (5000 examples) of the MNIST database of handwritten digits using a backpropagation variant suitable for nonvolatile memory (NVM) + selector crossbar arrays, obtaining a training (generalization) accuracy of 82.2% (82.9%). Using a neural network simulator matched to the ... View full abstract»

• ### Low-Frequency Noise and Random Telegraph Noise on Near-Ballistic III-V MOSFETs

Publication Year: 2015, Page(s):3508 - 3515
Cited by:  Papers (9)
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In this paper, we report the observation of random telegraph noise (RTN) in highly scaled InGaAs gate-all-around (GAA) MOSFETs fabricated by a top-down approach. RTN and low-frequency noise were systematically studied for devices with various gate dielectrics, channel lengths, and nanowire diameters. Mobility fluctuation is identified to be the source of 1/f noise. The 1/f noise was found to decre... View full abstract»

• ### Direct Observation of Self-Heating in III–V Gate-All-Around Nanowire MOSFETs

Publication Year: 2015, Page(s):3516 - 3523
Cited by:  Papers (10)
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Gate-all-around (GAA) MOSFETs use multiple nanowires (NWs) to achieve target $I_{mathrm{{scriptscriptstyle ON}}}$ , along with excellent 3-D electrostatic control of the channel. Although the self-heating effect has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and spec... View full abstract»

• ### Thin-Film Silicon Heterojunction FETs for Large Area and Flexible Electronics: Design Parameters and Reliability

Publication Year: 2015, Page(s):3524 - 3529
Cited by:  Papers (3)
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The design parameters and reliability of thin-film heterojunction FET (HJFET) devices comprised of hydrogenated amorphous Si (a-Si:H) gate-stacks on crystalline Si (c-Si) substrates are discussed. It is shown that the pinchoff voltage of the HJFET can be adjusted over a wide range of voltages, the gate leakage can be reduced both by improving the a-Si:H growth conditions and reducing the gate area... View full abstract»

• ### Pixel-Parallel 3-D Integrated CMOS Image Sensors With Pulse Frequency Modulation A/D Converters Developed by Direct Bonding of SOI Layers

Publication Year: 2015, Page(s):3530 - 3535
Cited by:  Papers (4)
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We have developed for the first time a 3-D integrated CMOS image sensor with pixel-parallel analog-to-digital converters (ADCs). Photodiode (PD) and inverter layers are prepared on separate silicon-on-insulator layers and directly bonded with damascened Au electrodes. The handle layer is then removed by grinding and XeF2 vapor phase etching to expose the PD surface. The developed process is suitab... View full abstract»

• ### A Solid-State Thin-Film Incandescent Light-Emitting Device

Publication Year: 2015, Page(s):3536 - 3540
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A new type of solid-state thin-film white light-emitting device has been reviewed and discussed. Light is emitted due to thermal excitation of the nano-sized conductive paths formed after the dielectric breakdown of the amorphous metal oxide thin film deposited on a silicon wafer. The mechanism of light emission, optical characteristics, reliability, driving methods, and efficiency are discussed. ... View full abstract»

• ### Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs

Publication Year: 2015, Page(s):3541 - 3546
Cited by:  Papers (7)
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This paper presents the impacts of an advanced shell doping profile (SDP) on the electrical characteristics of a junctionless (JL) FET in terms of OFF-current, subthreshold swing (SS), and ON-current by a numerical simulator. Due to the potential mirroring effect, a special observation stemming from the SDP, the carriers can enter the intrinsic region from the doped surface reducing the series res... View full abstract»

• ### Band Structure Effects in Extremely Scaled Silicon Nanowire MOSFETs With Different Cross Section Shapes

Publication Year: 2015, Page(s):3547 - 3553
Cited by:  Papers (9)
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A multiscale simulation package based on ab initio calculation is used to study the band structure effects in extremely scaled gate-all-around silicon nanowire (SNW) MOSFETs with different cross-sectional shapes. All the interactions are computed directly from ab initio method without semiempirical parameters, and the effects of crystal atom relaxations and boundary atom dangling bond saturations ... View full abstract»

• ### Systematic Characterization of Tunnel FETs Using a Universal Compact Model

Publication Year: 2015, Page(s):3554 - 3559
Cited by:  Papers (2)
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We propose a novel systematic procedure to individually characterize relevant physical phenomena that typify tunnel FETs (TFETs) in general. The procedure uses the Lambert $W$ function to explicitly solve the subthreshold and above-threshold transfer characteristics of TFETs, as described by a recently proposed universal TFET compact model based on Kane's tunneling formulation. The resulting expli... View full abstract»

• ### Impact of Asymmetric Configurations on the Heterogate Germanium Electron–Hole Bilayer Tunnel FET Including Quantum Confinement

Publication Year: 2015, Page(s):3560 - 3566
Cited by:  Papers (8)
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We investigate the effect of asymmetric configurations on the heterogate germanium electron-hole bilayer tunnel FET (TFET) and assess the improvement that they provide in terms of boosting the typically very low ON-current levels of TFET devices in the presence of field-induced quantum confinement. We show that when a very strong inversion for holes is induced at the bottom of the channel, the for... View full abstract»

• ### Germanium n-Channel Planar FET and FinFET: Gate-Stack and Contact Optimization

Publication Year: 2015, Page(s):3567 - 3574
Cited by:  Papers (5)
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We demonstrate Ge enhancement-mode nMOS FinFETs fabricated on 300-mm Si wafers, incorporating an optimized gate-stack (interface trap density Dit below 2 × 1011 eV-1 · cm-2), n+-doping (active doping concentration Nact exceeding 1 × 1020 cm-3), and metallization (contact resistivity Pc below 2 ×... View full abstract»

• ### Quantum Confinement Effects in Extremely Thin Body Germanium n-MOSFETs

Publication Year: 2015, Page(s):3575 - 3580
Cited by:  Papers (8)
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We explore the impact of varying channel thickness (from 8 to 1.5 nm) on extremely thin germanium n-MOSFETs, by explicitly incorporating the quantum confinement effects in the band structure calculations using the first principle density functional theory. In Ge (001) thin films in the sub-10-nm regime, the X valley becomes the lowest conduction band valley and is mostly responsible for the charge... View full abstract»

• ### A coarse-graining approach to rate equations of the composite AC-NBTI model

Publication Year: 2015, Page(s):3581 - 3587
Cited by:  Papers (2)
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For ac negative bias temperature instability (NBTI), the composite model that combines the reaction-diffusion (R-D) model for permanent component and the trap-detrap (T-D) model for recoverable component has almost been accepted. However, simple analytical formulas, which are useful for product qualification, have not yet been established. In this paper, we present a coarse-graining approach to an... View full abstract»

• ### General Geometric Fluctuation Modeling for Device Variability Analysis

Publication Year: 2015, Page(s):3588 - 3594
Cited by:  Papers (4)
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We propose a new modeling approach based on the impedance field method (IFM) to analyze the general geometric variations in device simulations. Compared with the direct modeling of multiple variational devices, the proposed geometric variation (GV) model shows a better efficiency thanks to its IFM-based nature. Compared with the existing random geometric fluctuation (RGF) model where the noise sou... View full abstract»

• ### 3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature

Publication Year: 2015, Page(s):3595 - 3604
Cited by:  Papers (9)
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Excellent electrostatic control offered by gate-all-around (GAA) geometry makes multinanowire (multi-NW) MOSFET a promising candidate for sub-10-nm technology nodes. Unfortunately, the GAA geometry is susceptible to the increased self-heating due to poor heat dissipation from the nanowires (NWs) to the substrate. Therefore, an understanding of spatio-temporal temperature rise, AT(x, y, z; t), at t... View full abstract»

• ### Multiscale statistically correlated variability: A unified model for computer-aided design

Publication Year: 2015, Page(s):3605 - 3612
Cited by:  Papers (1)
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A simple analytical model of statistically correlated variability that unifies local and global variations is presented. This model is compatible with computer-aided design (CAD) implementation, and covers device dimension-dependent mismatch, distance-dependent mismatch, and statistical across-chip variations in a single formulation. It is able to describe the effect of correlated variability sour... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy