IEEE Transactions on Components, Packaging and Manufacturing Technology

Filter Results

Displaying Results 1 - 25 of 26
• Front Cover

Publication Year: 2015, Page(s): C1
| |PDF (278 KB)
• IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

Publication Year: 2015, Page(s): C2
| |PDF (117 KB)

Publication Year: 2015, Page(s):1377 - 1378
| |PDF (132 KB)
• A Silicon Interposer Platform Utilizing Microfluidic Cooling for High-Performance Computing Systems

Publication Year: 2015, Page(s):1379 - 1386
Cited by:  Papers (3)
| |PDF (2403 KB) | HTML

In this paper, a silicon interposer platform using microfluidic cooling is proposed for high-performance computing systems. The key advantage of the the silicon interposer is its very fine-pitch wiring, which enables high-bandwidth off-chip signaling for the chips assembled on the silicon interposer. Compared with conventional air cooling, embedded microfuidic cooling is used for better cooling an... View full abstract»

• Low Thermal-Resistance Silicon-Based Substrate for Light-Emitting Diode Packaging

Publication Year: 2015, Page(s):1387 - 1392
Cited by:  Papers (1)
| |PDF (1234 KB) | HTML

In this paper, a low thermal-resistance packaging substrate for white light-emitting diodes (LEDs) which used a silicon substrate with cavities and through-silicon vias was designed, fabricated, and tested. The substrate was composed of a silver-layer-coated light-reflection cup and ultrathin silicon-based with micro through-vias filled with copper for electrical interconnection and heat dissipati... View full abstract»

• Fine-Grained 3-D IC Partitioning Study With a Multicore Processor

Publication Year: 2015, Page(s):1393 - 1401
Cited by:  Papers (4)
| |PDF (3561 KB) | HTML

Low power is widely considered as a key benefit of 3-D integrated circuits (ICs), yet there have been few thorough design studies on how to maximize power benefits in 3-D ICs. In this paper, we present design methodologies to reduce power consumption in 3-D ICs using a large-scale commercial-grade multicore microprocessor (OpenSPARC T2). To further improve power benefits in 3-D ICs on the top of t... View full abstract»

• Assembly and Packaging Technologies for High-Temperature and High-Power GaN Devices

Publication Year: 2015, Page(s):1402 - 1416
Cited by:  Papers (12)
| |PDF (3951 KB) | HTML

This paper gives a detailed analysis on the assembly and packaging technologies for the state-of-the-art GaN-based high-electron-mobility transistors, which are suitable for high-temperature and high-power applications. Silver sintering and transient liquid phase bonding were selected as die-attachment techniques, and gold and palladium were investigated for electrical interconnection materials. B... View full abstract»

• A Theoretical Study on Post-It-Like Debonding Process for BCB Cap Transfer Packaging Based on FEM Simulation

Publication Year: 2015, Page(s):1417 - 1422
Cited by:  Papers (2)
| |PDF (1410 KB) | HTML

This paper presents ANSYS finite-element method analysis of wafer-level Benzocyclobutene cap transfer packaging process utilizing simple and easy detachment of the carrier wafer. The detachment has been implemented through hydrophobic monolayer coating of Si carrier wafer surface before BCB cap patterning. Razor blade insertion between the Si carrier and device wafer is used to separate the BCB ca... View full abstract»

• Reliability of plastic-encapsulated electronic components in supersaturated steam environments

Publication Year: 2015, Page(s):1423 - 1431
Cited by:  Papers (1)
| |PDF (3156 KB) | HTML

Medical steam sterilizers use rapid cycles of temperature, humidity, and pressure to sterilize medical instruments. These cycles represent an exceptionally harsh environment for electronics and, currently, only metal can devices with high-reliability electronic components can be used to electronically monitor and verify the completeness of sterilization. The work presented in this paper has allowe... View full abstract»

• Nondestructive Characterization of Molecular Structures at Buried Copper/Epoxy Interfaces and Their Relationship to Locus of Failure Analysis

Publication Year: 2015, Page(s):1432 - 1440
Cited by:  Papers (5)
| |PDF (2170 KB) | HTML

Delamination at heterogeneous metal/polymer interfaces during reliability testing of packaged devices continues to be a reliability issue in microelectronic packaging. Although interfacial adhesion properties are largely determined by molecular structures at buried interfaces, structure-property relationships at buried metal/polymer interfaces are not well understood due to a lack of nondestructiv... View full abstract»

• Electrowetting Heat Pipes for Heat Transport Over Extended Distances

Publication Year: 2015, Page(s):1441 - 1450
Cited by:  Papers (5)
| |PDF (3790 KB) | HTML

The heat transport capacity of the conventional heat pipes over extended distances is limited by the maximum condensate flow that their wicks can sustain. This paper introduces and analyzes a new planar heat pipe technology, which can transport ultrahigh heat loads (>1 kW) over extended distances (>1 m). The concept of an electrowetting heat pipe (EHP) is based on replacing the adiabatic wic... View full abstract»

• Experimental Investigation of a Direct Liquid Immersion Cooled Prototype for High Performance Electronic Systems

Publication Year: 2015, Page(s):1451 - 1464
Cited by:  Papers (1)
| |PDF (2867 KB) | HTML

As the demand grows for electronics to become faster and more compact, the expectation for tomorrow's data center is no different. Like many of the current high performance data center installations, design considerations on all scales must be taken into account. The proposed solution does just this by looking at the entire cooling approach from the chip level all the way to the plenum level. The ... View full abstract»

• Heat Generation in Bond Wires

Publication Year: 2015, Page(s):1465 - 1476
Cited by:  Papers (2)
| |PDF (3699 KB) | HTML

Equations for fast and exact calculation of a simple model for heat transfer from a bond wire to a cylindrical finite mold package including nonideal heat transfer from wire to mold are presented. These allow for a characterization of an arbitrary mold/bond wire combination. The real mold geometry is approximated using the mold model cylinder radius and the thermal contact conductance of the mold/... View full abstract»

• Fast Structure-Aware Direct Time-Domain Finite-Element Solver for the Analysis of Large-Scale On-Chip Circuits

Publication Year: 2015, Page(s):1477 - 1487
Cited by:  Papers (1)
| |PDF (1675 KB) | HTML

A fast time-domain finite-element algorithm is developed for the analysis and the design of very large-scale on-chip circuits. The structure specialty of on-chip circuits, such as Manhattan geometry and layered permittivity, is preserved in the proposed algorithm. As a result, the large-scale matrix solution encountered in the 3-D circuit analysis is turned into a simple scaling of the solution of... View full abstract»

• Capacitance Expressions and Electrical Characterization of Tapered Through- Silicon Vias for 3-D ICs

Publication Year: 2015, Page(s):1488 - 1496
Cited by:  Papers (5)
| |PDF (2430 KB) | HTML

Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered through-silicon vias (T-TSVs) are proposed. The expressions are suitable for TSVs with high aspect ratio (thin and long). The maximum percentage errors between the calculated and simulated results for the insulator capacitance and the substrate capacitance are 1.86% and 3.75%, respectively. The... View full abstract»

• Analytical Formulas for Tradeoff Among Channel Loss, Length, and Frequency of $RC$ - and $LC$ -Dominant Single-Ended Interconnects for Fast Equalized Link Tradeoff Estimation

Publication Year: 2015, Page(s):1497 - 1506
| |PDF (3601 KB) | HTML

This paper presents simple and intuitive closed-form formulas for tradeoff among channel loss, length, and frequency of single-ended interconnects to aid fast equalized link tradeoff estimation. Based on a transfer function model for single-ended interconnects, we derived two closed-form tradeoff formulas for RC- and LC-dominant interconnects. The formulas' accuracies and computation time improvem... View full abstract»

• Impedance-Varying Broadband 90° Branch-Line Coupler With Arbitrary Coupling Levels and Higher Order Harmonic Suppression

Publication Year: 2015, Page(s):1507 - 1515
Cited by:  Papers (7)
| |PDF (2236 KB) | HTML

We propose a new design methodology to broaden the bandwidth of a single-section 90° branch-line coupler (BLC) with arbitrary coupling level. The method used here to broaden the BLC bandwidth is to replace conventional uniform transmission lines that would never be feasible in many implementations with nonuniform lines governed by a truncated Fourier series. Based on how impedances are prof... View full abstract»

• An Investigation of the Ink-Transfer Mechanism During the Printing Phase of High-Resolution Roll-to-Roll Gravure Printing

Publication Year: 2015, Page(s):1516 - 1524
Cited by:  Papers (7)
| |PDF (3227 KB) | HTML

Reducing the linewidth of electrodes is of high importance for increasing not only the efficiency of photovoltaic devices but also the performance of organic thin-film transistors. In particular, controlling the line pattern in printing processes has been difficult. In this paper, we report an analytical approach for obtaining high-resolution control over the ink-transfer mechanism in roll-to-roll... View full abstract»

• Failure Analysis and Experimental Verification for Through-Silicon-via Underfill Dispensing on 3-D Chip Stack Package

Publication Year: 2015, Page(s):1525 - 1532
Cited by:  Papers (2)
| |PDF (4123 KB) | HTML

In this paper, through-silicon-via (TSV) dispensing is introduced to address the underfill challenge for a 3-D chip stack package. An edge flood failure would form if the underfill flow breaks through the planar sidewalls of a 3-D package. The edge flood failure could lead to an incomplete underfill and the occupation of a huge area on the substrate. In order to avoid an edge flood, the encapsulan... View full abstract»

• Study of Techniques for Flip-Chip Bonding to Organic Substrates for Low-Power Applications

Publication Year: 2015, Page(s):1533 - 1540
Cited by:  Papers (2)
| |PDF (3381 KB) | HTML

This paper deals with the study of technologies for flip-chip assembly of CMOS integrated power converters on standard FR4 organic substrates. Tests for the characterization of commercially available technologies for microassemblies, such as anisotropic adhesive bonding, thermocompression bonding, thermosonic/ultrasonic bonding, and solder bonding, are carried out. The aim of this paper is to dete... View full abstract»

• Bondability of Second Copper Wire Bonds on Silver and Nickel-Palladium–Gold-Silver Metallization

Publication Year: 2015, Page(s):1541 - 1545
| |PDF (1319 KB) | HTML

Several types of metallization have been used in order to enhance the bondability of wire bond. The introduction of copper (Cu) wire bond further increases the requirement of finding the suitable metallization. In this paper, two types of metallization, namely silver (Ag) and nickel-palladium-gold-silver (Ni/Pd/Au/Ag), deposited on Cu substrate were used as the bond pad for the second Cu wire bond... View full abstract»

Publication Year: 2015, Page(s): 1546
| |PDF (2580 KB)
• how can you get your idea to market first

Publication Year: 2015, Page(s): 1547
| |PDF (3513 KB)
• Learning Has No Boundaries

Publication Year: 2015, Page(s): 1548
| |PDF (586 KB)
• IEEE Components, Packaging, and Manufacturing Technology Society information for authors

Publication Year: 2015, Page(s): C3
| |PDF (111 KB)

Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

Full Aims & Scope

Managing Editor
Ravi Mahajan
Intel