# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 23 of 23

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2015, Page(s): C2
| PDF (137 KB)
• ### A 2.4-GHz All-Digital PLL With a 1-ps Resolution 0.9-mW Edge-Interchanging-Based Stochastic TDC

Publication Year: 2015, Page(s):917 - 921
Cited by:  Papers (1)
| | PDF (1011 KB) | HTML

A 2.4-GHz all-digital phase-locked loop (ADPLL) for Zigbee application is presented. A stochastic time-to-digital converter (STDC) with an edge-interchange circuit (EIC) is proposed. The rising edges of the two input clocks of STDC are cyclically interchanged by EIC, which achieves dynamic element matching and doubles the equivalent number of arbiters in STDC. The frequency resolution of the LC-ba... View full abstract»

• ### A Band-Divided Memory Polynomial for Wideband Digital Predistortion With Limited Bandwidth Feedback

Publication Year: 2015, Page(s):922 - 926
Cited by:  Papers (4)
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With a real analog bandpass filter (BPF) in the feedback loop, band-limited digital predistortion (DPD) normally uses a narrower bandwidth low-pass filter at baseband to further constrain the bandwidth of the power amplifier (PA) output signal. This discards the nonlinear information at the BPF's roll-off regions. The PA's spectral regrowth at the edge of the BPF is thus unable to be suppressed wi... View full abstract»

• ### An Ultralow-Power Low-Noise CMOS Biopotential Amplifier for Neural Recording

Publication Year: 2015, Page(s):927 - 931
Cited by:  Papers (2)
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This brief presents a design strategy for a neural recording amplifier array with ultralow-power low-noise operation that is suitable for large-scale integration. The topology combines a highly efficient but supply-sensitive single-ended first stage with a shared reference channel and a differential second stage to effect feedforward supply noise cancellation, combining the low power of single-end... View full abstract»

• ### A Small-Area and Energy-Efficient 12-bit SA-ADC With Residue Sampling and Digital Calibration for CMOS Image Sensors

Publication Year: 2015, Page(s):932 - 936
Cited by:  Papers (1)
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This brief proposes a small-area and energy-efficient 12-bit successive approximation analog-to-digital converter (SA-ADC) for CMOS image sensors with a column-parallel readout structure. The proposed SA-ADC, which uses only a 6-bit capacitor digital-to-analog converter (DAC) for residue sampling, reduces the capacitor area to 1/64th of that for the 12-bit capacitor DAC and adopts the scaled refer... View full abstract»

• ### An Area-Efficient Current-Mode Bandgap Reference With Intrinsic Robust Start-Up Behavior

Publication Year: 2015, Page(s):937 - 941
Cited by:  Papers (1)
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During mass production, bandgap reference failure can cause chip failure, resulting in yield loss. A bandgap reference with robust start-up behavior is therefore needed. In this brief, the issue of multiple operating points is examined, along with a prior art low-voltage current-mode bandgap reference (CMBGR) structure. A CMBGR structure with only two stable operating points is proposed, which can... View full abstract»

• ### An Ultralow-Power Overcurrent Protection Circuit for Micropower Class D Amplifiers

Publication Year: 2015, Page(s):942 - 946
Cited by:  Papers (1)
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Although class D amplifiers (CDAs) are highly advantageous over their linear amplifier counterparts in terms of power efficiency, their power efficiency remains undesirably low at nominal operation conditions where the output power is ~26 dB lower than its peak output power (due to the large crest factor of the audio/speech signal and headroom for adjustment). This is particularly the case for pow... View full abstract»

• ### A Low-Leakage Body-Guarded Analog Switch in 0.35- $mumbox{m}$ BiCMOS and Its Applications in Low-Speed Switched-Capacitor Circuits

Publication Year: 2015, Page(s):947 - 951
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A low-leakage body-guarded analog switch (BGswitch) for slow switched-capacitor (SC) circuits is presented. The improvement of accuracy in SC circuits employing BG-switches is demonstrated by comparing their performance with counterparts employing conventionally biased CMOS switches in three applications: sample-and-hold (S/H) amplifier, SC amplifier, and highvoltage drain-extended MOSFET (DEMOS).... View full abstract»

• ### A 40-MHz Bandwidth 0–2 MASH VCO-Based Delta-Sigma ADC With 35-fJ/Step FoM

Publication Year: 2015, Page(s):952 - 956
Cited by:  Papers (1)
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This brief presents a nonlinearity-cancelation technique in a 0-2 MASH voltage-controlled oscillator (VCO)-based delta-sigma (ΔΣ) analog-to-digital converter (ADC), where the VCO's distortion is substantially mitigated in a power-efficient way. A dual-input VCO-based quantizer topology is also proposed to implement a low-power multiple-input adder and integrator, with nox penalty in ... View full abstract»

• ### Subsampling Models of Bandwidth Mismatch for Time-Interleaved Converter Calibration

Publication Year: 2015, Page(s):957 - 961
Cited by:  Papers (2)
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Bandwidth mismatch is one of the mechanisms that reduce linearity in time-interleaved analog-to-digital converters (TI-ADCs). Models of bandwidth mismatch have been already proposed in the literature: this brief extends them to subsampling signals, validates them against circuit-level simulations, and investigates their effect on linearity in subsampling applications. The effectiveness of two prev... View full abstract»

• ### Enhanced Grounded Capacitor Multiplier and Its Floating Implementation for Analog Filters

Publication Year: 2015, Page(s):962 - 966
Cited by:  Papers (1)
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A current-mode capacitor multiplier using a differential amplifier with exponential current scaling is presented. The proposed circuit consists of a reduced implementation of a multiplier based on differential amplifiers with decreased need for parameter matching compared with a conventional structure, thus reducing the power consumption and silicon area. It includes an exponential current scaling... View full abstract»

• ### Hardware Reduction of MASH Delta-Sigma Modulator Based on Partially Folded Architecture

Publication Year: 2015, Page(s):967 - 971
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This brief presents a new multistage noise-shaping (MASH) structure that has less hardware by applying partially folded architecture. A folded MASH architecture that exploits adders in half is introduced, and the proposed architecture combines the folded MASH architecture and the conventional MASH architecture. The noise power spectrum of the proposed architecture is mathematically analyzed and th... View full abstract»

• ### A Novel and Efficient Design for an RSA Cryptosystem With a Very Large Key Size

Publication Year: 2015, Page(s):972 - 976
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This brief presents a novel and efficient design for a Rivest-Shamir-Adleman (RSA) cryptosystem with a very large key size. A new modular multiplier architecture is proposed by combining the fast Fourier transform-based Strassen multiplication algorithm and Montgomery reduction, which is different from the interleaved version of Montgomery multiplications used in traditional RSA designs. Anew modu... View full abstract»

• ### Digital Implementation of a Single Dynamical Node Reservoir Computer

Publication Year: 2015, Page(s):977 - 981
Cited by:  Papers (1)
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Minimal hardware implementations of machine-learning techniques have been attracting increasing interest over the last decades. In particular, field-programmable gate array (FPGA) implementations of neural networks (NNs) are among the most appealing ones, given the match between system requirements and FPGA properties, namely, parallelism and adaptation. Here, we present an FPGA implementation of ... View full abstract»

• ### A Novel Approach to Design Low-Cost Two-Stage Frequency-Response Masking Filters

Publication Year: 2015, Page(s):982 - 986
Cited by:  Papers (1)
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The multistage frequency-response masking (FRM) technique is widely used to reduce the complexity of a filter when the transition bandwidth is extremely small. In this brief, a real generalized two-stage FRM filter without any constraint on the subfilters or the interpolation factors was proposed. New principles and equations were deduced to determine the design parameters. The subfilters were the... View full abstract»

• ### Sharp Corner/Edge Recognition in Domestic Environments Using RGB-D Camera Systems

Publication Year: 2015, Page(s):987 - 991
Cited by:  Papers (1)
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This brief proposes a sharp corner/edge detection and evaluation scheme for RGB-D camera-based domestic applications. The proposed approach first preprocesses the original depth map of objects in domestic environments captured by an RGB-D camera system and then uses the recovered depth map to recognize sharp corners/edges on objects and calculate their sharpness. Furthermore, the approaching speed... View full abstract»

• ### A Proportionate Diffusion LMS Algorithm for Sparse Distributed Estimation

Publication Year: 2015, Page(s):992 - 996
Cited by:  Papers (5)
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We propose a new diffusion least mean squares algorithm that utilizes adaptive gains in the adaptation stage for the sparse distributed estimation problem. We derive the optimal gains that attain a minimum mean-square deviation and propose an adaptive gain control method. We provide the mean stability analysis to establish sufficient condition for the algorithm to converge in the mean sense. The a... View full abstract»

• ### Ultimate Boundedness of Nonautonomous Dynamical Complex Networks Under Impulsive Control

Publication Year: 2015, Page(s):997 - 1001
Cited by:  Papers (3)
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This brief is concerned with the ultimate boundedness problem of nonautonomous complex networks with different dynamical nodes by using the impulsive control method. Some ultimate boundedness and asymptotical stability criteria for the nonautonomous complex networks with different dynamical nodes under impulsive control are obtained by using Lyapunov functions. The results show not only that unsta... View full abstract»

• ### Complete Stability of Neural Networks With Nonmonotonic Piecewise Linear Activation Functions

Publication Year: 2015, Page(s):1002 - 1006
Cited by:  Papers (1)
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This brief studies the complete stability of neural networks with nonmonotonic piecewise linear activation functions. By applying the fixed-point theorem and the eigenvalue properties of the strict diagonal dominance matrix, some conditions are derived, which guarantee that such n-neuron neural networks are completely stable. More precisely, the following two important results are obtained: 1) The... View full abstract»

• ### Leader-Following Consensus in Second-Order Multiagent Systems via Event-Triggered Control With Nonperiodic Sampled Data

Publication Year: 2015, Page(s):1007 - 1011
Cited by:  Papers (4)
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The problem of leader-following consensus in second-order multiagent systems is investigated in this brief, where the data are sampled randomly within a certain known bound and the data transmission is driven by an event-triggered control protocol. A distributed event-triggered control protocol is designed, in which the Zeno behavior is naturally excluded by the strictly positive sampling interval... View full abstract»

• ### IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

Publication Year: 2015, Page(s): 1012
| PDF (38 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2015, Page(s): C3
| PDF (33 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org