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Electron Devices, IEEE Transactions on

Issue 7 • Date Jul 1994

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Displaying Results 1 - 25 of 31
  • High frequency simulation of resonant tunneling diodes

    Publication Year: 1994 , Page(s): 1098 - 1111
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1172 KB)  

    The small and large-signal response of the resonant tunneling diode at high-frequencies is studied using a quantum simulator. The Poisson and Schrodinger equations are solved self-consistently for each harmonic using the harmonic balance technique. This ensures that the total current, consisting of the displacement plus conduction currents, is conserved across the device for each harmonic. The RTD exhibits an increased capacitance in the negative differential conductance (NDC) region in agreement with experimental data. As recently proposed this capacitance increase results from the formation of an emitter well capacitor when the well discharges. The derivation of the RTD capacitance from a quasi-static analysis using the differential variation of the de charge in the RTD is shown to be not applicable because the RTD well charges through the cathode but discharges through the anode. The frequency dependence of the conductance and susceptance is similar to reported experimental data. A large frequency dependence of the admittance is only observed when the RTD is biased in the negative differential conductance (NDC) region. These calculations predict an effective reduction of the RTD conductance and capacitance at high-frequency in the NDC region. This effect can be modeled using a quantum inductance in series with the negative resistance of the RTD as recently proposed. Due to the simultaneous reduction of both the conductance and the capacitance at high-frequency in the NDC region the maximum frequency of oscillation does not differ much from its estimate using the low frequency conductance and capacitance. The large-signal response at high-frequency of an RTD biased in the negative differential region is also presented in this paper. The large-signal negative-conductance is shown to decrease with both increasing frequency and ac voltage View full abstract»

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  • A high-packing density pixel with punchthrough read-out method for an HDTV interline CCD

    Publication Year: 1994 , Page(s): 1128 - 1135
    Cited by:  Papers (2)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB)  

    A new pixel structure for a high-packing-density interline CCD is proposed, in which signal charges are read out from the photodiodes to the vertical CCD by a punchthrough mechanism. This read-out method makes it possible to reduce the depth of the VCCD channel and the second p-well by implanting these two layers after diffusion of the photodiode n layer. Spreading resistance measurements on dummy wafers show that the depths of these layers are 0.28 μm and 0.6 μm, respectively. Moreover, the photodiode n-layer is covered with a surface p+-layer, even at the transfer region. We describe the results of simulations and experiments on a test image sensor with pixel dimensions of 7.3 μm (H)×7.6 μm (V). From the experimental data, we estimate the characteristics of an image sensor with pixel dimension 5.0 μm (H)×5.2 μm (V). Such a device should have a maximum charge handling capability of 1.4×105 electrons, a smear level of -88 dB, a sensitivity of 1.5×103 electrons/Ix with a 30% fill factor, no image lag, and a low photodiode dark signal of less than 14 electrons at 60°C. These results indicate that an IL-CCD with a punchthrough readout structure is suitable for image sensors with a high pixel density such as 2/3 inch 2 million pixel image sensors for high-definition TV applications View full abstract»

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  • Optical characterization of diamond MIS capacitors

    Publication Year: 1994 , Page(s): 1265 - 1272
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    The transient photoresponse properties of diamond metal-insulator-semiconductor (MIS) capacitors have been characterized for the first time. Capacitors were fabricated on natural diamond using an electrochemical cleaning step with a CVD SiO2 dielectric and an optional carbon implantation to create a nonuniform doping profile. Devices were found to function as integrating photodetectors and were evaluated by the spectral dependence of the transient photocapacitance (PC). We discuss a model that distinguishes between the responses due to inversion layer population and that due to bulk trap occupancy changes. Inversion charge generation was observed at all wavelengths investigated and it dominated the PC transient at photon energies above 3 eV. Possible reasons for this result are discussed and analyzed. We could not demonstrate a suitable way to use carbon implantation to form a surface n-type layer in a MIS device without degrading the device IV properties and eliminating the integrating photoresponse observed on non-implanted devices. These results suggest that diamond charge-storage devices can function only if the diamond surface is prepared properly before device fabrication View full abstract»

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  • A model for the time- and bias-dependence of p-MOSFET degradation

    Publication Year: 1994 , Page(s): 1184 - 1196
    Cited by:  Papers (19)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1136 KB)  

    Physical properties of both electron trapping and detrapping are identified to influence the degradation behavior of p-MOS transistors. Focusing on electron trapping first, we find as a decisive feature a spatially growing region of filled traps in the vicinity of the drain. Due to an exponential decrease of the electron injection current as a function of distance to the drain, its length grows logarithmically over time resulting in a logarithmic time dependence of the degradation. The logarithmic growth of this region is proven by means of charge-pumping experiments, whereas the logarithmic time dependence of the degradation itself is readily visible in the transistor current. Including electron-detrapping, the model permits a consistent description of both time- and bias-dependence of the degradation thereby leading to an improved expression for the lifetime of p-MOS transistors View full abstract»

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  • Degradation of gain in bipolar transistors

    Publication Year: 1994 , Page(s): 1083 - 1091
    Cited by:  Papers (9)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    In this paper hot carrier related aging of n-p-n bipolar transistors is investigated experimentally and theoretically in order to bring physical insight into the bipolar hFE (common emitter current gain) degradation. Electrical stress experiments are performed on transistors with different base doping profiles at varying temperatures. Detailed process simulations are performed to determine the doping profiles of the base-emitter junction. Monte Carlo transport simulations are then performed at different temperatures and bias conditions to determine the electron and hole distribution functions in the base-emitter junction. AT&T's 0.8 μm BICMOS technology is used to fabricate the experimental bipolar structures. For this non-self aligned technology we attribute hFE degradation to the presence of hot holes and secondary electrons which are generated by hot hole impact ionization. This feedback due to impact ionization has a dominant effect on the high energy tails of the distribution of both holes and electrons even when the overall current multiplication is low. Simple hot electron energy transport models do not contain the complexity to properly describe ionization feedback and carrier heating, and are therefore inadequate. An exponential dependence of the transistor lifetime on BVEBO is deduced for constant voltage stress (Vstress<BVEBO) conditions, confirming the importance of secondaries in the process of degradation View full abstract»

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  • An accelerated life test method for highly reliable on-board TWT's with a coated impregnated cathode

    Publication Year: 1994 , Page(s): 1297 - 1300
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    An accelerated life-test method is established for on-board TWT's with an M-type cathode. This method is shown to be effective to predict the TWTs reliability. The M-type cathode has two life-limiting factors: impregnant reduction and surface coating degradation. The theoretical calculations of these factors under the accelerating conditions are confirmed by the life-test results. The highest acceleration is obtained at the cathode temperature of 1100 °CB with the cathode current density of 0.6 A/cm2. In this case the acceleration factor is derived to be 31. The lifetime distribution of TWT's at the optimum cathode temperature is predicted using the derived acceleration factors. The Weibull distribution of BTTs (beam test tubes) fits a line with a slope of 3.2. From this result, TWT's with an M-type cathodes at optimum cathode temperature show wear-out failure and their cumulative failure rate is under 0.5% during a useful life of 100 000 h View full abstract»

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  • Theoretical study of the effect of an AlGaAs double heterostructure on metal-semiconductor-metal photodetector performance

    Publication Year: 1994 , Page(s): 1112 - 1119
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    The impulse and square-wave input response of different GaAs metal-semiconductor-metal photodetector (MSM) designs are theoretically examined using a two dimensional drift-diffusion numerical calculation with a thermionic-field emission boundary condition model for the heterojunctions. The rise time and the fall time of the output signal current are calculated for a simple GaAs, epitaxially grown, MSM device as well as for various double-heterostructure barrier devices. The double heterostructure devices consist of an AlGaAs layer sandwiched between the top GaAs active absorption layer and the bottom GaAs substrate. The effect of the depth of the AlGaAs layer on the speed and responsivity of the MSM devices is examined. It is found that there is an optimal depth, at fixed applied bias, of the AlGaAs layer within the structure that provides maximum responsivity at minimal compromise in speed View full abstract»

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  • 0.25 μm gate length CMOS devices for cryogenic operation

    Publication Year: 1994 , Page(s): 1179 - 1183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    Under cryogenic operation, a low Vth realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low Vth. Double implanted MOSFET's technology was employed to achieve the low Vth while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at Vdd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below View full abstract»

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  • Modeling of the hot electron subpopulation and its application to impact ionization in submicron silicon devices-Part II: numerical solutions

    Publication Year: 1994 , Page(s): 1206 - 1212
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    A macroscopic transport model for the hot electron subpopulation (HES) and a nonlocal impact ionization (II) model were proposed in Part I of this article: see ibid. p. 1200, 1994. The transport equations have been derived from the Boltzmann transport equation (BTE) and closure has been provided by an empirically determined equation. The transport equations and the II model have been calibrated using data obtained from self-consistent Monte Carlo (SCMC) simulations. In this article we present the numerical solutions obtained by applying the proposed model to n+- n--n+ structures with various doping profiles. The results are compared to the data obtained from SCMC simulations and also to those obtained from models proposed earlier by other authors View full abstract»

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  • Hole mobility measurements in heavily doped Si1-xGex strained layers

    Publication Year: 1994 , Page(s): 1273 - 1281
    Cited by:  Papers (2)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (876 KB)  

    Both Hall and drift in-plane mobilities have been measured in compressively strained p-type Si1-xGex layers grown by both chemical vapor deposition (CVD) and molecular beam epitaxy (MBE). Measurements were taken over the boron doping range of 1018 cm-3 to 1020 cm-3 with Ge contents of 0⩽x⩽0.22. The apparent drift mobility is found to increase with increasing Ge content, whereas the Hall mobility decreases for the same samples at all doping levels studied. The Hall factor decreases with increasing Ge content, which may be due to additional scattering mechanisms introduced by Ge along with changes in the valence band structure as a result of strain. In this study we also provide the first report of Hall mobility measurements of deuterium-passivated, heavily doped Si View full abstract»

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  • The characteristics of the lateral IGBT on the thin SOI film when the collector voltage of the IGBT is applied to the substrate

    Publication Year: 1994 , Page(s): 1301 - 1302
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    The characteristics of the lateral IGBT on an SOI film when the collector voltage of the IGBT is applied to the substrate are investigated for its application to a high side switch. The measurements of the blocking capability and the dynamic latch-up current during the turn-off transient under an inductive load are carried out with varying thicknesses of the SOI film. A 260 V IGBT can be fabricated on a 5 μm thick SOI film without the special device structure. The dynamic latch-up current is improved by reducing the SOI film thickness. This paper shows that applying the collector voltage of the IGBT to the substrate makes it possible to improve the characteristics of the IGBT on a thin SOI film View full abstract»

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  • An all-implanted, self-aligned, GaAs JFET with a nonalloyed W/p+-GaAs ohmic gate contact

    Publication Year: 1994 , Page(s): 1078 - 1082
    Cited by:  Papers (4)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB)  

    We describe a self-aligned, refractory metal gate contact, enhancement mode, GaAs junction field effect transistor (JFET) where all impurity doping was done by ion implantation. Processing conditions are presented for realizing a high gate turn-on voltage (~1.0 V at 1 mA/mm of gate current) relative to GaAs MESFET's. The high gate turn-on voltage is the result of optimizing the p+-gate implant and anneal to achieve a nonalloyed ohmic contact between the implanted p+-GaAs and the sputter deposited tungsten gate contact. Initial nominally 1.0 μm×50 μm n-JFET's have a transconductance of 85 mS/mm and ft of 11.4 GHz View full abstract»

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  • A novel technology for a-Si TFT-LCD's with buried ITO electrode structure

    Publication Year: 1994 , Page(s): 1120 - 1124
    Cited by:  Papers (2)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    A novel process technology for a-Si TFT-LCD's with the buried ITO electrode (BI) structure was developed and applied to 10-in-diagonal LCD panels. By employing the BI structure, an aperture ratio of 29% was achieved in high resolution panels with a pixel size of 192 μ and the pixel defect density was reduced to about one third of the conventional structure. The defect reduction effect of the BI structure was also confirmed theoretically. The BI structure provides significant advantages for high-performance TFT-LCD's View full abstract»

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  • A study on the effect of the gate contact geometry and dimensions on ESD failure threshold level of power MOSFET's

    Publication Year: 1994 , Page(s): 1282 - 1287
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    The effect of the gate contact geometry and dimensions on the catastrophic electrostatic discharge (ESD) failure of power MOSFET's that have ESD protection circuits between their gate and source has been studied. This paper describes the relationship between the ESD failure threshold level and the gate contact width of MOSFET's. It has been found from numerical analysis that only the area near the gate contact, and not the entire gate, is sensitive to the ESD pulse, because the diffusion of the ESD charge into the inner region is suppressed by the sheet resistance of the gate polycrystalline silicon (poly-Si) film. It is also shown here that widening the gate contact and carefully designing the shape of the gate contact, as well as lowering the gate poly-Si sheet resistance, substantially enhance the ESD failure threshold level of power MOSFET's because a greater portion of an ESD charge can diffuse into the gate region of the device View full abstract»

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  • A fully complementary BiCMOS technology for 10 V mixed-signal circuit applications

    Publication Year: 1994 , Page(s): 1149 - 1160
    Cited by:  Papers (3)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (892 KB)  

    A 10 V fully complementary BiCMOS technology, HBC-10, has been developed for high speed, low noise and high precision mixed signal system integration applications. In this technology, two varieties of CMOS transistors have been implemented for 10 V analog and 5 V digital applications. A gate oxide thickness of 30 nm is utilized for the 10 V CMOS transistors with a lightly doped drain extension added to the NMOS structure to achieve device lifetime in excess of 10 years. A gate oxide thickness of 18 nm is used for 5 V CMOS logic circuits. These transistors are specially architected so that they may also serve as analog transistors in 5 V circuit applications. The 5 V NMOS transistor lifetime is guaranteed by use of a double diffused drain structure. The active devices are isolated by a fully recessed 1.5 μm oxide grown under high pressure conditions. Use of high pressure steam, plus combining diffusion operations where possible, results in a low overall thermal budget. This allows the up-diffusion of buried layers to be minimized so that a thin, 1.6 μm epitaxial silicon layer is sufficient to support 10 V bipolar transistors. The resultant vertical PNP and NPN transistors are characterized with cut-off frequencies of more than 1.3 GHz and 5 GHz, respectively. Likewise, the associated products of the current gain and Early voltage of PNP and NPN bipolar transistors are more than 1000 and 6000 V, respectively. A precision, buried Zener diode (for voltage reference applications), PtSi Schottky diode, polysilicon-oxide-polysilicon capacitor and trimmable thin film resistor are integrated into this process. This wide variety of passive and active components is essential for system integration and has been carefully designed for precision analog applications. The total number of masking operations is 23, which includes double layer metallization View full abstract»

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  • Theory and application of charge pumping for the characterization of Si-SiO2 interface and near-interface oxide traps

    Publication Year: 1994 , Page(s): 1213 - 1216
    Cited by:  Papers (66)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    A generalized charge pumping model has been developed which extends the use of charge pumping from a study of traps at the Si-SiO 2 interface to a study of traps in the oxide. The analytical model, based on tunneling theory, allows the spatial distribution of near-interface oxide traps to be determined from variable frequency charge pumping data. Profiling of near-interface oxide traps in irradiated MOSFET's as well as SONOS nonvolatile memory devices is presented View full abstract»

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  • Operating principle of dual collector magnetotransistors studied by two-dimensional simulation

    Publication Year: 1994 , Page(s): 1136 - 1148
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1252 KB)  

    Dual collector magnetotransistors are magnetic-field-sensitive devices currently developed in several laboratories. Optimized sensor design is often attempted by trial and error rather than by established design rules. This motivated the present comprehensive study of the operation of magnetotransistors by accurate two-dimensional numerical simulations. We model vertical and lateral transistors as obtained by industrial IC technology on the basis of data provided by the chip manufacturer. We consider the entire device structure with the full, complex device geometry, and the physically proper boundary conditions. Our simulations reveal the details, controversial hitherto, of the operating principle of these devices. In particular we find that, in the case of the vertical transistor, it is essentially the emitter injection modulation effect which dominates the sensor response. In the case of the lateral transistor, the magnetic sensitivity is predominantly determined by minority-carrier deflection, though side effects are involved as well. By variation of the doping profile and the device geometry we derive rules for optimized magnetotransistor design View full abstract»

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  • Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure

    Publication Year: 1994 , Page(s): 1222 - 1226
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB)  

    A gate-overlapped LDD structure was introduced to ultra-thin SOI MOSFET's in order to overcome the degradation in source-to-drain breakdown voltage (BVds) due to a parasitic bipolar action. By reductions in drain electric field and parasitic resistance at a source n- region, the BVds was improved with almost the same current drivability as that in single drain structure. The behavior of the BVds on LDD n- concentration was investigated by use of a numerical device simulator, and it was found that the electric field at a lower portion of the n- region, which forms the current path, was relaxed effectively at an optimum n- doping condition View full abstract»

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  • Hot-electron degradation in NMOSFET's: results from temperature anneal

    Publication Year: 1994 , Page(s): 1303 - 1305
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    0.6 μm N-channel MOSFET's are hot-electron stressed at Vg =Vd=8 V, t=103 s to produce large changes in device saturation drain current Id, linear channel conductance gd, maximum transconductance gm, subthreshold slope S, and threshold voltage shift Vt. Isochronal post-stress anneal up to 300°C depopulates the trapped electrons, resulting in substantial recovery of the hot-electron degradation to within 10% of the pre-stress value. Gate-to-drain capacitance reveals that interface traps, which are also generated in significant numbers, are only partially annealed. These results provide direct confirmation that trapped electrons rather than interface traps are mainly responsible for degradation in the following NMOSFET device parameters:Id, gd, gm, S, Vt View full abstract»

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  • The influence of the semiconductor and dielectric properties on surface flashover in silicon-dielectric systems

    Publication Year: 1994 , Page(s): 1233 - 1238
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    New experimental results on surface flashover are reported for high field silicon-dielectric systems. Different conditions of the lateral surface, contacts and ambient dielectrics have been studied. The strong influence of the semiconductor quality, and that of the dielectric properties, on the prebreakdown and breakdown response of the system, is demonstrated. All experimental results strongly support the conclusion that surface flashover in silicon systems is a physical process totally different from semiconductor surface breakdown. This conclusion has important practical application in the improvement of the performance of photoconductive power switches, severely limited by premature breakdown effects View full abstract»

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  • High frequency performance of SiC heterojunction bipolar transistors

    Publication Year: 1994 , Page(s): 1092 - 1097
    Cited by:  Papers (7)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    A compact heterojunction bipolar transistor (HBT) model was employed to simulate the high frequency and high power performances of SiC-based bipolar transistors. Potential 6H-SiC/3C-SiC heterojunction bipolar transistors (6H/3C-HBT's) at case temperatures of 27°C (300 K) through 600°C (873 K) were investigated. The high frequency and high power performance was compared to AlGaAs/GaAs HBT's. As expected, the ohmic contact resistance limits the high frequency performance of the SiC HBT. At the present time, it is only possible to reliably produce 1×10-4 Ω-cm2 contact resistances on SiC, so an fT of 4.4 GHz and an fmax of 3.2 GHz are the highest realistic values. However, assuming an incredibly low 1×10-6 Ω-cm2 contact resistance for the emitter, base, and collector terminals, an fT of 31.1 GHz and an fmax of 12.7 GHz can be obtained for a 6H/3C-SiC HBT View full abstract»

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  • Design of traveling wave tubes based on field theory

    Publication Year: 1994 , Page(s): 1288 - 1296
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB)  

    A method is described for the design of helix traveling wave tubes (TWT) which is based on the linear field analysis of the coupled beam-wave system. The dispersion relations are obtained by matching of radial admittances at boundaries instead of the individual field components. This approach provides flexibility in modeling various beam and circuit configurations with relative ease by choosing the appropriate admittance functions for each case. The method is illustrated for the case of a solid beam inside a sheath helix which is loaded externally by lossy dielectric material, a conducting cylinder, and axial vanes. Extension of the analysis to include a thin tape helix model is anticipated in the near future. The TWT model may be divided into axial regions to include velocity tapers, lossy materials and severs, with the helix geometry in each region varied arbitrarily. The relations between the AC velocities, current densities, and axial electric fields are used to derive a general expression for the new amplitudes of the three forward waves at each axial boundary. The sum of the fields for the three forward waves (two waves in a drift region) is followed to the circuit output. Numerical results of the field analysis are compared with the coupled-mode Pierce theory. A method is suggested for applying the field analysis to accurate design of practical TWT's that have a more complex circuit geometry, which starts with a simple measurement of the dispersion of the helix circuit. The field analysis may then be used to generate a circuit having properties very nearly equivalent to those of the actual circuit View full abstract»

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  • A novel temperature-stable light-emitting diode

    Publication Year: 1994 , Page(s): 1125 - 1127
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    A new type of light-emitting diode (LED) has been developed, the light intensity of which is stable during temperature change. This device consists of a multilayer dielectric optical filter on the surface of a conventional LED. The transmissivity of the optical filter is low for the short wavelength region of the LED's light spectrum and high for the long wavelength region. When the LED's temperature increases, the spectrum of LED light shifts toward the long wavelength side because of the shrinkage of the energy gap of the compound semiconductor. The shift increases the total transmission of the light because the transmissivity is high for the long wavelength region. This increase compensates for the decrease of the LED light intensity, which is caused by the decrease of the internal quantum efficiency. The effect of this filter is confirmed by both calculation and experiment View full abstract»

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  • Detailed characterization and analysis of the breakdown voltage in fully depleted SOI n-MOSFET's

    Publication Year: 1994 , Page(s): 1217 - 1221
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    The breakdown voltage in fully depleted SOI n-MOSFET's has been studied over a wide range of film thicknesses, channel dopings, and channel lengths. In lightly-doped films, the breakdown voltage roll-off at shorter channel lengths becomes much less severe as the film thickness is reduced. This is a result of improved resistance to punchthrough and DIBL effects in thinner SOI. Consequently, at channel lengths below about 0.8 μm, ultrathin (50 nm) SOI can provide better breakdown voltages than thicker films. At heavier doping levels the punchthrough and DIBL are suppressed, and there is little dependence of breakdown voltage on film thickness. Two-dimensional simulations have been used to investigate the breakdown behavior in these devices. It is found that the drain-induced barrier lowering affects the breakdown voltage both directly, via punchthrough, and indirectly through its effect on the current flow and hole generation in the high-field regions View full abstract»

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  • Effects of temperature and defects on breakdown lifetime of thin SiO2 at very low voltages

    Publication Year: 1994 , Page(s): 1227 - 1232
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    This paper investigates the physics of voltage and temperature accelerated breakdown testing of silicon dioxide within the framework of an anode hole injection model which can predict low voltage (3.3 V and below) breakdown lifetime. The field acceleration rate is shown to be independent of temperature, while the reduction of oxide breakdown lifetime at increased temperature is due to the oxide's enhanced susceptibility to damage caused by the holes' transport through the oxide. This paper also investigates defect related breakdown, showing that defects can be mathematically modeled as effective thinning even for aggressively scaled oxides. The effective thickness statistic derived from ramp breakdown or high-field lifetime or charge-to-breakdown tests enables determination of the oxide integrity of a specific oxide technology. For 3.3 V operation, an oxide technology must provide an effective thickness of 44 Å; for 2.5 V operation, 34 Å View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego