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IEEE Transactions on Computers

Issue 7 • Date July 1994

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Displaying Results 1 - 12 of 12
  • Comments on "An optimal shortest-path routing policy for network computers with regular mesh-connected topologies"

    Publication Year: 1994, Page(s):862 - 863
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (143 KB)

    S. Badr and P. Podar (1989) introduced a zig-zag routing policy and showed its optimality for shortest-path routing on square or infinite grid networks with independent link failures. This paper shows that, contrary to the claim of Badr and Podar, a zig-zag policy is not optimal for shortest-path routing on torus networks.<> View full abstract»

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  • Bit-level systolic array for fast exponentiation in GF(2m)

    Publication Year: 1994, Page(s):838 - 841
    Cited by:  Papers (16)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    This paper presents a new parallel-in-parallel-out bit-level systolic array with unidirectional data flow for computing exponentiation in GF(2m). The array is highly regular, modular, and thus well suited to very-large-scale-integration implementation. In addition, it can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. As compared w... View full abstract»

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  • Diagonal and toroidal mesh networks

    Publication Year: 1994, Page(s):815 - 826
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    Diagonal and toroidal mesh are degree-4 point to point interconnection models suitable for connecting communication elements in parallel computers, particularly multicomputers. The two networks have a similar structure. The toroidal mesh is popular and well-studied whereas the diagonal mesh is relatively new. In this paper, we show that the diagonal mesh has a smaller diameter and a larger bisecti... View full abstract»

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  • Algorithm-based fault tolerance for FFT networks

    Publication Year: 1994, Page(s):849 - 854
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    Algorithm-based fault tolerance (ABFT) is a low-overhead system-level fault tolerance technique. Many ABFT schemes have been proposed in the past for fast Fourier transform (FFT) networks. In this paper, a new ABFT scheme for FFT networks is proposed. We show that the new approach maintains the high throughput of previous schemes, yet needs lower hardware overhead and achieves higher fault converg... View full abstract»

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  • Performance modeling and evaluation of circuit switching using Clos networks

    Publication Year: 1994, Page(s):854 - 861
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    Call packing has been recognized as a routing scheme that significantly reduces the blocking probability of connection requests in a circuit-switched Clos multistage interconnection network. In this paper, for the first time, we develop general analytical models for the point-to-point blocking probability of the call-packing scheme applied to Clos networks. By introducing a new parameter called th... View full abstract»

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  • A family of efficient regular arrays for algebraic path problem

    Publication Year: 1994, Page(s):769 - 777
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    The method of decomposing a dependence graph into multiple phases with an appropriate m-phase schedule function is useful for designing faster regular arrays for matrix multiplication and transitive closure. In this paper, we further apply this method to design several parallel algorithms for the algebraic path problem and derive N×N 2D regular arrays with execution times [9N/2]-2 (for the c... View full abstract»

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  • Fault tolerance in a class of sorting networks

    Publication Year: 1994, Page(s):827 - 837
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB)

    The early study of fault tolerance in efficient sorting networks only achieved single-fault tolerance. By eliminating critical comparators, L. Rudolph (1985) presented a 1-fault tolerant design of the balanced sorting network (BSN) at the cost of one redundant stage of N/2 comparators and two permuters external to the network. In this paper, we show, however, that 1-fault tolerance of BSN can be a... View full abstract»

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  • Hypercube communication delay with wormhole routing

    Publication Year: 1994, Page(s):806 - 814
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    We present an analytical model for the performance evaluation of hypercube computers. This analysis is aimed at modeling a deadlock-free wormhole routing scheme prevalent on second generation hypercube systems. Probability of blocking and average message delay are the two performance measures discussed. We start with the communication traffic to find the probability of blocking. The traffic analys... View full abstract»

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  • Design and evaluation of hardware strategies for reconfiguring hypercubes and meshes under faults

    Publication Year: 1994, Page(s):841 - 848
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    This paper discusses the design of two reconfiguration strategies for distributed memory multicomputer architectures under failures. The specific architectures to which we apply the techniques are hypercubes and meshes. The first scheme uses spare processors attached to certain processors in the hypercube or mash using a novel embedding technique. The second approach places spare processors along ... View full abstract»

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  • Performance analysis of multilevel bus networks for hierarchical multiprocessors

    Publication Year: 1994, Page(s):789 - 805
    Cited by:  Papers (5)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1288 KB)

    A multiple bus system provides more bandwidth and a high degree of fault tolerance than a single bus system. But such a system becomes very expensive for a large number of processors and memory modules, due to the requirement of too many connections (switches). Lang (1983) proposed a different bus-based system, known as the partial multiple bus system, which requires a lower number of connections ... View full abstract»

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  • Election in asynchronous complete networks with intermittent link failures

    Publication Year: 1994, Page(s):778 - 788
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1060 KB)

    Considers the problem of fault-tolerant leader election in asynchronous complete (fully-connected) distributed networks. The processors are reliable, but some of the communication channels may fail intermittently before or during the execution of the algorithm. Channel failures are undetectable due to the asynchronous nature of the network. Let n be the number of processors in the network and f be... View full abstract»

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  • Addendum to “Hierarchical scalable photonic architectures for high-performance processor interconnection”

    Publication Year: 1994
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB)

    The above paper by L. Bhuyan and D.P. Agrawal (1984) described a hierarchical, all-optical wavelength division multiplexed (WDM) network that is being built to support the communication requirements of a large distributed shared memory system. Dynamically adaptable bandwidth allocation is supported, both within and between levels of the hierarchy, and is highly scalable through wavelength re-use a... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org