By Topic

Solid-State Circuits, IEEE Journal of

Issue 6 • Date Jun 1994

Filter Results

Displaying Results 1 - 17 of 17
  • Noise in digital dynamic CMOS circuits

    Page(s): 655 - 662
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Impact of clock slope on true single phase clocked (TSPC) CMOS circuits

    Page(s): 723 - 726
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    Clocked digital circuits are sensitive to changes of the input signals close to the clock transitions. Non ideal properties of the clock transition, such as slope, make timing requirements more complicated. Here we present methods, quantitative limits and clock buffer requirements by studying clock slope impact on TSPC circuits. The investigation is based on SPICE simulations of edge-triggered D flip-flops and latches, implemented in the TSPC technique. The simulation results were also verified by measurements on 2-μm CMOS prescalers View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-power, area-efficient digital filter for decimation and interpolation

    Page(s): 679 - 687
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB)  

    The area and power consumption of oversampled data converters are governed largely by the associated digital decimation and interpolation filters. This paper presents a low-power, area-efficient, mask-programmable digital filter for decimation and interpolation in digital-audio applications. Several architectural and implementation features reduce the complexity of the filter and allow its realization in a die area of only 3670 mils2 (2.37 mm2) in a 1-μm CMOS technology. The use of simple multiplier-free arithmetic logic and a new memory addressing scheme for multi rate digital filters results in a power consumption of only 18.8 mW from a 5-V supply and 6.5 mW from a 3-V supply. The memory addressing scheme and the programmable functionality of the filter are general enough to implement a wide class of FIR and IIR single-rate and multi-rate digital filters View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A BiCMOS low-power current mode gate

    Page(s): 741 - 745
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    A controllable BiCMOS low-power current mode logic (LPCML) gate is proposed. The LPCML can be controlled to operate in a high-power mode when its inputs and outputs are in transition. When the gate is idle, it is in a low-power mode and the circuit maintains its output levels with very little tail current. A circuit implementation of the LPCML is also reported with a discussion on its design considerations. A circuit implementation of the LPCML with conventional CML indicates that its delay is greater than that of CML by about 60%. The power consumption of LPCML is proportional to the time it spends in the high-power mode, and, hence, may be significantly lower than that of CML View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A GaAs up converter integrated circuit for a double conversion cable TV “set-top” tuner

    Page(s): 688 - 692
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    A GaAs up converter integrated circuit used for a double conversion cable TV “set-top” tuner is described. The up converter IC converts the 50 to 550 MHz band to an IF of 700 MHz. The IC meets the linearity and noise figure requirements for a cable TV tuner. It includes an AGC and image reject filter. The reduced component count achieved by using an integrated circuit and the resulting reduction in the size of the tuner, provides potential cost savings over a discrete implementation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling

    Page(s): 693 - 700
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than VDD. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 μm BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay

    Page(s): 646 - 654
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB)  

    An improved model for the ramp response of a CMOS inverter has been derived where the influences of the short-circuit current and the input-to-output coupling capacitance are considered. These effects modify the ideal linear relationship between the inverter propagation delay and the input ramp rise/fall time by adding a term proportional to the charge supplied by the short-circuiting transistor. This term is shown to contain first- and second-order contributions of the input ramp rise/fall time where the second-order contribution effectively models the propagation delay roll-off for slow input ramps. Both the first and the second-order effects are found to be affected by the P-to-N-channel gain ratio. The model shows excellent agreement with SPICE level 3 simulations; even when the short-circuiting transistor has a driving capability twice that of the charging/discharging transistor the error in the propagation delay is only about 2% for a slow input ramp (input-to-output slope-ratio at VDD/2 equal to 1:2) View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A charge recycle refresh for Gb-scale DRAM's in file applications

    Page(s): 715 - 722
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 μm technology. After amplification in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is 60% of the conventional. This scheme is further extended for application to n arrays with 1/n data-line current dissipation. Moreover, the multi-array activation with charge recycle refresh is proposed, in which the same peak current as in the conventional scheme is achieved with a small number of refresh cycles for refreshing all the cells View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design, measurement and analysis of CMOS polysilicon TFT operational amplifiers

    Page(s): 727 - 732
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    The small signal properties of polysilicon TFT opamps have been investigated in this paper. A method for the scaling of gm (transconductance) and gds (output conductance) has been proposed, facilitating their estimates for various transistors in operational amplifiers. The analysis of two CMOS opamps fabricated by a low temperature, glass compatible poly-Si TFT process is demonstrated in comparison to the measured performance. The first implementation has been internally compensated with high load-driving capability (up to 36 pF), while the second one has employed a cascode stage for increased gain (56 dB) View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A BiCMOS time interval digitizer based on fully-differential, current-steering circuits

    Page(s): 707 - 714
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    A time interval digitizer cell with a 0-16 ns input range and a nominal LSB width of 1.0 ns has been integrated in a 2-μm BiCMOS technology, The circuit exhibits both integral and differential nonlinearity below 0.15 LSB and a timing error of 0.32 ns RMS. Logic gate propagation delays are used as time measurement units, and the nominal value of the delays is set by an on-chip phase-locked loop (PLL). Fully-differential, current-steering circuits with low voltage swings are used to implement the time interval digitizer so as to generate minimal switching noise. The cell is to be used in the monolithic, multi-channel realization of a high-sensitivity, mixed-signal data acquisition front-end. By virtue of the time digitization architecture used, the average power dissipation of the cell is only 19.8 mW, despite the use of circuits that dissipate static power, and the layout area is a compact 448 μm×634 μm View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A four-quadrant CMOS analog multiplier for analog neural networks

    Page(s): 746 - 749
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 μm CMOS process. Experimental results obtained from it are presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CMOS four-quadrant multiplier using bias feedback techniques

    Page(s): 750 - 752
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    A new wide-range CMOS four-quadrant multiplier using the bias feedback techniques is presented. Simulation results show that for a power supply of ±5 V, the linear range is over 14 V and the linearity error is less than 1% over a 13 V input range. Experimental results show that the linear range is over ±1 V. The results will be useful in analog signal processing applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A wideband low-noise variable-gain BiCMOS transimpedance amplifier

    Page(s): 701 - 706
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    A new monolithic variable gain transimpedance amplifier is described. The circuit is realized in BiCMOS technology and has measured gain of 98 kΩ, bandwidth of 128 MHz, input noise current spectral density of 1.17 pA/√(Hz) and input signal-current handling capability of 3 mA View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power consumption estimation in CMOS VLSI chips

    Page(s): 663 - 670
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom design. Also comparisons between static and dynamic logic are given. Results show that the power consumption of all interconnections and off chip driving can be up to 20% and 65% of the total power consumption respectively. Compared to cell library design, gate array designed chips consume about 10% more power, and power reduction in full custom designed chips could be 15% View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-frequency fifth order switched-current bilinear elliptic lowpass filter

    Page(s): 737 - 740
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    Design considerations for and measured results of a prototype high-frequency fifth order switched-current bilinear elliptic lowpass filter are presented in this paper. The prototype filter was implemented on a standard 1.2 μm double-metal single-polysilicon CMOS process and occupied a total die area of 1.5 mm2. When clocked at 2 MHz, the filter achieved a passband edge of 350 kHz, a stopband edge of 420 kHz, a passband ripple of 0.6 dB and a minimum stopband attenuation of 26 dB. With a single 5 V power supply the filter consumed 28 mW View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Highly testable design of BiCMOS logic circuits

    Page(s): 671 - 678
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    Most of the work reported in the literature to date on the testability of BiCMOS circuits has concentrated on fault characterization and the need for a suitable testing method that can address the peculiarities of BiCMOS circuits. The problem of adequately testing large BiCMOS logic networks remains open and complex. In this paper, we introduce a new design for testability technique for BiCMOS logic gates that results in highly testable BiCMOS logic circuits. The proposed design incorporates two features: a test charge/discharge path and built-in current sensing (BICS). The test charge/discharge path is activated only during testing and facilitates the testing of stuck-open faults using single test vectors. BICS facilitates testing of faults that cause excessive IDDQ. HSPICE simulation results show that the proposed design can detect stuck-open faults at a test speed of 10 MHz. Faults causing excessive IDDQ are detected by BICS with a detection time of 1 ns and a settling time of 2 ns. Impact of the proposed design on normal operation is minimal. The increase in propagation delay in normal operation is less than 3%. This compares very favorably with CMOS BICS reported in the literature, where the propagation delay increase was 20%, 14.4% respectively. The increase in the area is less than 15% View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A static memory cell based on the negative resistance of the gate terminal of p-n-p-n devices

    Page(s): 733 - 736
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    We propose a new static memory cell that is based on bistable operation of a three-terminal p-n-p-n device working in the blocking state. The bistable operation is verified by the measurements of Si/amorphous Si prototypes. The experimental prototypes achieve delay times in the nanosecond range when operating with external gate and anode resistors. In order to decrease the power consumption of the memory cell, we propose to operate it with MOS transistor switches instead of the gate resistors. The memory cell can be integrated into VLSI processes, and is of a size suitable for VLSI applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan