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IEEE Transactions on Industrial Electronics

Issue 2 • May 1989

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Displaying Results 1 - 21 of 21
  • The VLSI circuit test problem-a tutorial

    Publication Year: 1989, Page(s):111 - 116
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (725 KB)

    Defect-free integrated circuits (IC) cannot be guaranteed by VLSI circuit manufacturers. Circuit complexity, IC defect anomalies, and economic considerations prevent complete validation of VLSI circuits. These VLSI test problems are especially acute in high-reliability designs and will only worsen as IC circuit size increases. Designers of IC, board, and system projects must be aware of the diffic... View full abstract»

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  • Fundamentals of testability-a tutorial

    Publication Year: 1989, Page(s):117 - 128
    Cited by:  Papers (14)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1468 KB)

    A review is presented of electrical testing, failure mechanisms, fault models, fault simulation, testability analysis, and test-generation methods for CMOS VLSI circuits. The relationships between the most commonly used fault models are explored. Various fault simulation methods are contrasted. The basic mechanisms used in test-vector generation are illustrated by examples. The importance of testa... View full abstract»

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  • Design for testability and built-in self test: a review

    Publication Year: 1989, Page(s):129 - 140
    Cited by:  Papers (19)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1136 KB)

    A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and... View full abstract»

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  • Microprocessor testability

    Publication Year: 1989, Page(s):151 - 163
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1455 KB)

    As the level of microprocessor complexity increases to several hundred thousand transistors for a single-chip machine, it is becoming very difficult to test commercially available designs to the level of fault coverage desired by some customers. In order to achieve near 100-percent coverage of single stuck-at faults, future microprocessors must be designed with special testing features (designed f... View full abstract»

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  • A custom hybrid GaAs driver and sensor device for a high-speed test system

    Publication Year: 1989, Page(s):175 - 184
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB)

    A customized hybrid GaAs device has been designed and prototyped that can operate from DC to 100 MHz and above, interface directly with ECL (emitter-coupled logic), TT (transistor-transistor logic), and CMOS components, and handle both the in-circuit and device testing environments. The circuits for both the driver and sensor are delineated, and some of the design issues are discussed. The prototy... View full abstract»

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  • IC quality and test transparency

    Publication Year: 1989, Page(s):197 - 202
    Cited by:  Papers (62)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (635 KB)

    It is shown that extremely high single-stuck fault coverage is necessary for high-quality products. Even 100% single-stuck fault coverage may not guarantee adequate quality. Results are presented that extend previous work and show that for high required IC quality, process yield has a negligible effect on required test thoroughness. The extensions consist of: removing the assumption of a one-to-on... View full abstract»

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  • Incoming test strategy based upon in-process failure and repair costs

    Publication Year: 1989, Page(s):203 - 210
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (720 KB)

    An economic model is developed that challenges traditional statistical quality control methods in the factory. Incoming inspection levels can be determined as a function of both the PPM failure rates and the lot-to-lot stability. Since current incoming failure rates have fallen two orders of magnitude to below 100 PPM, the model can be used to re-evaluate conventional test strategies in high-volum... View full abstract»

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  • Quiescent power supply current measurement for CMOS IC defect detection

    Publication Year: 1989, Page(s):211 - 218
    Cited by:  Papers (106)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (851 KB)

    Quiescent power supply current (I/sub DDQ/) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, I/sub DDQ/ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set tha... View full abstract»

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  • Design for testability of analog/digital networks

    Publication Year: 1989, Page(s):227 - 230
    Cited by:  Papers (27)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB)

    The testing of analog/digital integrated circuits is difficult since they allow direct access to relatively few signals. Since the probing of component pins is the fundamental chip production test technique (and possibly that of board test as well, i.e. in-circuit test), methods must be found to enhance the controllability and observability of internal signal networks. The authors provide a set of... View full abstract»

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  • A universal test and maintenance controller for modules and boards

    Publication Year: 1989, Page(s):231 - 240
    Cited by:  Papers (15)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1060 KB)

    The design of a versatile module test and maintenance controller (MMC) is presented. Driven by structures test programs, an MMC is able to test every chip in a module or PCB via a test bus. More than one test bus can be controlled by an MMC, and can support several bus architectures and many modes of testing. The differences between MMCs on different modules are the test programs that they execute... View full abstract»

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  • Design of self-diagnostic boards by signature analysis

    Publication Year: 1989, Page(s):241 - 245
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    The authors present a single-faulty-chip diagnostic technique which requires only two reference signatures for any number of chips on the original board. With this technique, it is possible to reduce substantially the hardware overhead compared to the diagnostic technique based on separate testing of each chip on the board. The technique can be also used for identification of faulty printed boards... View full abstract»

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  • An efficient built-in self testing for random-access memory

    Publication Year: 1989, Page(s):246 - 253
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (685 KB)

    The authors propose a test algorithm for pattern-sensitive faults in large-size RAM with high circuit density. The algorithm tests an n-bit RAM in 195 square root n time to detect both static and dynamic pattern-sensitive faults over the 9-neighbourhood of every memory cell. A 4 Mb RAM can be tested by the proposed algorithm several thousand times faster than the conventional sequential algorithms... View full abstract»

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  • Testability of parity checkers

    Publication Year: 1989, Page(s):254 - 262
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    Checkers are used in digital circuits to detect both intermittent and stuck-at faults. The most common error detectors are parity checkers. Such circuits are themselves subject to failures. The use of parity trees is outlined, and techniques for testing them are surveyed. The effect of the checker's structure on its testability is discussed. Several fault models are considered: single stuck-at, mu... View full abstract»

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  • Automated synthesis for testability

    Publication Year: 1989, Page(s):263 - 277
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1508 KB)

    The authors present an integrated, compiler-driven approach to digital chip design that automates mask layout and test-pattern generation for 100% stuck-at fault coverage. This approach is well suited for designs where it is most important the minimize the design cycle time rather than the silicon area. The authors show that by compiling from a unified design specification followed by logic synthe... View full abstract»

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  • The Test Engineer's Assistant: a design environment for testable and diagnosable systems

    Publication Year: 1989, Page(s):278 - 285
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (807 KB)

    The Test Engineer's Assistant (TEA) is a set of computer-aided design (CAD) tools that helps the system design engineer meet testability requirements by construction. TEA addresses system design for testability at all levels of the design hierarchy, the lowest level being the board level. The design is represented as a graph where each node indicates a hardware component (or chip on a board) and e... View full abstract»

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  • Linking design and test tools: an implementation

    Publication Year: 1989, Page(s):286 - 295
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (898 KB)

    A computer-aided test analysis system was designed to appraise the testability of logic systems and to provide the functional specification of the test programs. To provide a helpful tool for both designers and test engineers, it was necessary to fully integrate this tool in a CAD (computer-aided design) system so that testability might be a design parameter and to automate the test-program produc... View full abstract»

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  • In-circuit test fixture [PCB testing]

    Publication Year: 1989, Page(s):192 - 196
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Deficiencies in the conventional in-circuit fixture are presented. A novel fixture is described, and quantitative comparisons are presented. Crosstalk is decreased by 60 dB, and transmission-line matching is possible View full abstract»

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  • Statistical fault sampling

    Publication Year: 1989, Page(s):141 - 150
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (876 KB)

    Computational requirements often discourage, or even prohibit, complete fault simulation of circuit designs having greater than 20000 single stuck-at faults. To circumvent this problem, statistical sampling methods have been proposed that provide fault coverage values within a small, predictable error range by simulating only a fraction of the circuit's total faults and using the result fault cove... View full abstract»

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  • Calculating the effective pattern rate for high-speed board test applications

    Publication Year: 1989, Page(s):164 - 174
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    A complex interplay of tester specifications can force in-circuit and functional board test systems to operate at less than their specified maximum pattern rates in real-world test applications. The author explores the factors that combine to limit test speed. He develops models for calculating the effective pattern rate based on tester performance data and the characteristics of the VLSI board un... View full abstract»

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  • Integrated pin electronic for a VLSI test system

    Publication Year: 1989, Page(s):185 - 191
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    Drivers, comparators, active loads, and per-pin timing circuitry for a VLSI test system are placed in two CMOS integrated circuits. This level of integration allows fast, low-capacitance pin electronics to be manufactured at relatively low cost. Novel design and calibration techniques are used to overcome limitations of CMOS technology View full abstract»

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  • Analog/digital ASIC design for testability

    Publication Year: 1989, Page(s):219 - 226
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    The author addresses three issues in design for testability (DFT) for mixed analog/digital application-specific integrated circuit (ASIC) chips: controllability, observability, and completeness in testing. These are examined for commonly used analog functions, and the results culminate in an architecture for testable mixed analog and digital circuits. The architecture is designed to solve the prob... View full abstract»

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Aims & Scope

IEEE Transactions on Industrial Electronics encompasses the applications of electronics, controls and communications, instrumentation and computational intelligence for the enhancement of industrial and manufacturing systems and processes.

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Meet Our Editors

Editor-in-Chief
Leopoldo Garcia Franquelo
Escuela Superior de Ingenieros
Universidad de Sevilla
Camino de los Descubrimientos s/n
41092 Sevilla, Spain
lgfranquelo@ieee.org
Phone: +34 954 48 73 65