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# IEEE Journal of Solid-State Circuits

## Filter Results

Displaying Results 1 - 25 of 41
• ### Optimization-based transistor sizing

Publication Year: 1988, Page(s):400 - 409
Cited by:  Papers (110)  |  Patents (10)
| | PDF (1185 KB)

A combined heuristic and mathematical programming approach to transistor sizing is presented. A fast heuristic algorithm is used to obtain an initial sizing of the circuit and convert the transistor sizing problem into a nonlinear optimization problem. The problem is then solved, in spaces of reduced dimensionality, by mathematical programming techniques. To cope with the nondifferentiability of t... View full abstract»

• ### A knowledge-based test generator for standard cell and iterative array logic circuits

Publication Year: 1988, Page(s):428 - 436
Cited by:  Papers (4)
| | PDF (900 KB)

The use of Prolog for test generation is discussed and an implementation in Prolog of an automatic test generator, Protean, for stuck-at faults in scan-designed standard cell VLSI circuits and iterative logic arrays is described. Protean comprises a cell test generator, which generates test knowledge and propagation characteristics for cells, and a hierarchical test generator, which uses this high... View full abstract»

• ### Measurement of the local latch-up sensitivity by means of computer-controller scanning electron microscopy

Publication Year: 1988, Page(s):597 - 603
Cited by:  Papers (4)
| | PDF (1189 KB)

The scanning electron microscopy (SEM) technique for the study of the local sensitivity to latch-up of CMOS integrated circuits is discussed. The technique is independent of a particular electric firing mechanism of latchup and does not require in-depth electrical characterization of the IC before the analysis. The electron beam in the SEM is adopted as a localized current injector, and the inject... View full abstract»

• ### A 45-Mbit/s CMOS VLSI digital phase aligner

Publication Year: 1988, Page(s):323 - 328
Cited by:  Papers (6)  |  Patents (16)
| | PDF (556 KB)

An eight-channel, 45-Mb/s digital phase aligner (DPA) has been fabricated in 2-μm CMOS. The device receives asynchronous serial data at a known average clock frequency and unknown phase, and phase-aligns it with a local clock of the same frequency for subsequent synchronous processing. The all-digital architecture of this device minimizes the need for external components and avoids reliance on ... View full abstract»

• ### A multimode PCM transceiver chip for 1.544-Mbit/s digital telecommunications

Publication Year: 1988, Page(s):318 - 322
| | PDF (412 KB)

A 1.25-μm CMOS VLSI device that converts the popular 1.544-Mb/s T1 format used in digital telecommunications to a 4.096-Mb/s system format is described. The transmit and receive functions are implemented with a RAM, a 3088-bit shift register, and 33 K transistors View full abstract»

• ### A 6 K GaAs gate array with fully functional LSI personalization

Publication Year: 1988, Page(s):581 - 590
Cited by:  Papers (1)
| | PDF (1060 KB)

A 12×12 multiplier consisting of 19000 devices was successfully implemented on a 6000-gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160°C range. The backgating and dynamic (switching) noise are also discussed as the key noise-ma... View full abstract»

• ### A 70-MHz 1.2-μm CMOS 16-point DFT processor

Publication Year: 1988, Page(s):343 - 350
Cited by:  Papers (6)
| | PDF (752 KB)

A chip architecture designed to compute a 16-point discrete Fourier transform (DFT) using S. Winograd's algorithm (1978) every 457 ns is presented. The 99500-transistor 1.2-μm chip incorporates arithmetic, control, and input/output circuitry with testability and fault detection into a 144-pin package. A throughput of 2.3×1012 gate-Hz/cm2 and 79-million multiplication... View full abstract»

• ### CMOS analog front end of a transceiver with digital echo cancellation for ISDN

Publication Year: 1988, Page(s):311 - 317
Cited by:  Papers (6)  |  Patents (8)
| | PDF (672 KB)

A CMOS analog front-end which contains a novel pulse-shaping circuit, an extremely linear-line-driver state, an oversampling second-order noise-shaping coder, and a wake-up signal detector is discussed. An analog front-end for 4B 3T coded signals is realized in a 2.5-μm CMOS technology and operates up to 4.5 km with 0.4-mm-diameter lines, needing only one 5-V power supply. It is possible to tra... View full abstract»

• ### 1.3-μm CMOS/bipolar standard cell library for VLSI computers

Publication Year: 1988, Page(s):500 - 506
Cited by:  Papers (26)
| | PDF (748 KB)

The CMOS/bipolar standard cell library has been enhanced from 2 to 1.3 μm for application to VLSI computers, such as 32-bit supermini- and microcomputers. This library has macrocells such as a 256-kb/8.4-ns ROM, 32-bit/4.5-ns carry propagation circuits for a 32-bit ALU, 4-kbyte/17-ns cache memory including an address translation function, and a 64-bit/37-ns multiplier. High integration density ... View full abstract»

• ### A deterministic algorithm for automatic CMOS transistor sizing

Publication Year: 1988, Page(s):522 - 526
Cited by:  Papers (7)  |  Patents (6)
| | PDF (384 KB)

A model which offers a closed-form equation for determining device size, based on speed and load, has been developed. The need for circuit simulation is eliminated in most cases. This model is used in a system for automatically producing performance-tuned cell layouts View full abstract»

• ### Test generation for data-path logic: the F-path method

Publication Year: 1988, Page(s):421 - 427
Cited by:  Papers (53)  |  Patents (1)
| | PDF (716 KB)

Tests for data-path logic can be generated with the aid of high-level methods that utilize the presence of special forms of sensitized paths. These paths, called fault paths (F-paths), are defined so that they transmit fault information with certainty. Their presence can be determined from the functional definition of a block, and when, exceptionally, they are absent, a minimum hardware a... View full abstract»

• ### A GaAs 4-bit adder-accumulator circuit for direct digital synthesis

Publication Year: 1988, Page(s):573 - 580
Cited by:  Papers (9)  |  Patents (5)
| | PDF (1174 KB)

A GaAs depletion-mode MESFET integrated circuit which is implemented with buffered FET logic and contains 155 gates is described. The chip is composed of a 4-bit adder, a 4-bit register, and lookahead-carry logic capable of connecting up to four chips in a 16-bit parallel adder-accumulator circuit for direct digital synthesis of a sinewave. Fully functional chips have been fabricated by a GaAs fou... View full abstract»

• ### A wafer-scale 170000-gate FFT processor with built-in test circuits

Publication Year: 1988, Page(s):336 - 342
Cited by:  Papers (39)
| | PDF (680 KB)

The wafer-scale 170000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using... View full abstract»

• ### Design of an image edge detection filter using the Sobel operator

Publication Year: 1988, Page(s):358 - 367
Cited by:  Papers (99)  |  Patents (13)
| | PDF (892 KB)

The architecture of the edge detector presented is highly pipeline to perform the computations of gradient magnitude and direction for the output image samples. The chip design is based on a 2-μm, double-metal, CMOS technology and was implemented using a silicon compiler system in less than 2 man-months. It is designed to operate with a 10-MHz two-phase clock, and it performs approximately 200&... View full abstract»

• ### A low-frequency GaAs MESFET circuit model

Publication Year: 1988, Page(s):605 - 608
Cited by:  Papers (41)  |  Patents (7)
| | PDF (244 KB)

GaAs MESFETs exhibit low-frequency anomalies which effect the performance of broadband systems. A four-terminal large-signal GaAs MESFET circuit model which predicts may of the low-frequency anomalies discovered in GaAS MESFETs is proposed. The four-terminal model accurately models drain lag', frequency dependence of the output resistance, and hysteresis. This model when implemented in a circuit ... View full abstract»

• ### The process engineer's workbench

Publication Year: 1988, Page(s):377 - 386
Cited by:  Papers (17)
| | PDF (740 KB)

A workstation-based implementation of a software system aimed at VLSI fabrication process synthesis is described. The system provides a versatile user interface to a number of process design aids, and incremental simulation capability, and an attractive graphical display of simulation results View full abstract»

• ### A 20-ns 256 K×4 FIFO memory

Publication Year: 1988, Page(s):490 - 499
Cited by:  Papers (7)  |  Patents (33)
| | PDF (880 KB)

A 256 K×4 FIFO (first-in-first-out) CMOS memory with 20-ns access time and 30-ns cycle time is described. To accomplish full static and asynchronous operation, signal synchronizer and arbiter circuits have been developed and implemented into the device. A pair of 120-word×4-bit static memories are furnished to provide 20-ns data access from the very first read cycle. The average curren... View full abstract»

• ### A 150 K channelless gate array design in 0.5-μm CMOS technology

Publication Year: 1988, Page(s):520 - 522
Cited by:  Papers (2)
| | PDF (344 KB)

The chip presented was designed as a vehicle to investigate the advantages and tradeoffs of using 0.5-μm technology for semicustom VLSI devices. The use of 0.5-μm technology requires that a 3.3-V supply be used. Several architectures were investigated for maximum efficiency and ease of use with place and route software, keeping in mind tradeoffs between routability, performance, and density.... View full abstract»

• ### ThunderBird: a complete standard cell layout package

Publication Year: 1988, Page(s):410 - 420
Cited by:  Papers (15)  |  Patents (2)
| | PDF (1036 KB)

The generalized standard cell layout style handled by ThunderBird is characterized by horizontal rows of standard cells with pads placed around the periphery of the chip. Furthermore, macro blocks may be present on the chip. The standard cells are permitted to have varying heights. The two key components of ThunderBird are TimberWolf3.2, a standard cell placement and global routing package, and th... View full abstract»

• ### A 1.5-GHz programmable divide-by-N GaAs counter

Publication Year: 1988, Page(s):480 - 484
Cited by:  Papers (5)
| | PDF (600 KB)

A GaAs divide-by-N programmable counter has been fabricated for use in microwave frequency synthesizers and other applications. The counter uses a 1-μm depletion-mode MESFET process. The counter is typically capable of dividing an input frequency of DC to 1.5 GHz by any divisor from 3 to 64 over a temperature range of -60 to 100°C. Input and output translators are incorporated to r... View full abstract»

• ### A self-terminating low-voltage swing CMOS output driver

Publication Year: 1988, Page(s):457 - 464
Cited by:  Papers (37)  |  Patents (126)
| | PDF (728 KB)

A CMOS output pad driver circuit is described that automatically series-terminates a driven line in the line's characteristic impedance. The circuit has advantages in speed, power, and size over conventional designs. The key idea is the use of emitter-coupled logic (ECL) compatible low-voltage swings for signaling, combined with the use of the driver transistor as both a switch and as a terminatio... View full abstract»

• ### Analytical modeling of the CMOS-like a-Si:H TFT inverter circuit

Publication Year: 1988, Page(s):566 - 572
Cited by:  Papers (5)
| | PDF (500 KB)

The transfer characteristics of a CMOS-like hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) inverter circuit are analyzed. Accurate analytical expressions for the sheet conductance of the ambipolar a-Si:H TFT are simplified and applied to the CMOS-like TFT inverter circuit. The inverter circuit is composed of only one type of ambipolar a-Si:H TFT that is used for both the driver a... View full abstract»

• ### A versatile data string-search VLSI

Publication Year: 1988, Page(s):329 - 335
Cited by:  Papers (21)  |  Patents (27)
| | PDF (700 KB)

A versatile data string-search VLSI has been fabricated using 1.6-μm CMOS technology. The VLSI consists of an 8 K content addressable memory (CAM) and a 20 K-gate finite-state automation logic (FSAL). A number of unique functions, such as strict/approximate-match string search and fixed/variable-length don't care' operations, were implemented. A total of 217600 transistors have been integrated... View full abstract»

• ### A subnanosecond Josephson 16-bit ALU

Publication Year: 1988, Page(s):591 - 596
Cited by:  Papers (14)
| | PDF (736 KB)

The design and characteristics of a Nb based Josephson 16-bit arithmetic logic unit (ALU) for use as a major component of a practical Josephson microprocessor are discussed. The ALU has 900 gates and uses dual-rail logic to perform 12 functions. One of the simplest algorithms, the ripple-carry method, is used. Experiments confirmed that ALU functions operated correctly. The critical path delay tim... View full abstract»

• ### Cascadable one/two-dimensional digital convolver

Publication Year: 1988, Page(s):351 - 357
Cited by:  Papers (6)
| | PDF (656 KB)

An architecture and a design for a high-speed CMOS digital convolver which can be used for real-time one-dimensional (1-D) and two-dimensional (2-D) signal processing are presented. In the 2-D mode this device can be used to convolve 10-bit image data with a 3×3 or 2×5 2-D eight-bit-per-coefficient impulse response at 20 M samples/s throughput. In 1-D applications it can be used as a t... View full abstract»

## Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Jan Craninckx
Imec
Kapeldreef 75
B-3001 Leuven, Belgium
jssc.craninckx@gmail.com