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Computers and Digital Techniques, IEE Proceedings E

Issue 3 • Date May 1989

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Displaying Results 1 - 9 of 9
  • Universal logic design algorithm and its application to the synthesis of two-level switching circuits

    Publication Year: 1989 , Page(s): 171 - 177
    Cited by:  Papers (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (644 KB)  

    The paper presents Thelen's algorithm (1981) and its application to the (1981) problems which arise in the logic design of two-level multiple-output switching circuits. The paper shows that the logic minimisation procedures, such as the expansion of implicants, detection of essential primes, computation of a minimal cover and reduction of prime implicants can be reduced to one problem and efficien... View full abstract»

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  • Algorithms for software implementations of RSA

    Publication Year: 1989 , Page(s): 166 - 170
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (328 KB)  

    Two new algorithms that facilitate the implementation of RSA in software are described. Both algorithms are essentially concerned with performing modular arithmetic operations on very large numbers, which could be of potential use to applications other than RSA. One algorithm performs modular reduction and the other performs modular multiplication. Both algorithms are based on the use of look-up t... View full abstract»

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  • 2D systolic solution to discrete Fourier transform

    Publication Year: 1989 , Page(s): 211 - 216
    Cited by:  Papers (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (484 KB)  

    A number of systolic architectures have appeared over the past few years for performing the discrete Fourier transform (DFT) and fast Fourier transform (FFT) algorithms, using both linear and orthogonal processing networks. The paper shows how a rectangular array of N CORDIC (co-ordinate digital computer) processing elements can be used to carry out an efficient two-dimensional systolic implementa... View full abstract»

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  • Parallel merge module for combining sorted lists

    Publication Year: 1989 , Page(s): 161 - 165
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (491 KB)  

    This paper presents a novel n-way parallel merge module (PMM) that consists of many parallel merge elements (PME) built into the tree structure, to enhance the throughput of hardware merger. The proposed parallel merge module can be used as a passive high speed module to match the data processing rate of other parallel hardware module, such as parallel sorter and data filters, in the backend compu... View full abstract»

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  • Adaptive, low latency, deadlock-free packet routing for networks of processors

    Publication Year: 1989 , Page(s): 178 - 186
    Cited by:  Papers (2)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1034 KB)  

    In order to provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented, which provide the propagation of data from processor to processor, based on addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements, namely deadlock and livelock freedom, good hot-spot performance, high throu... View full abstract»

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  • Yield estimation for serial superchip

    Publication Year: 1989 , Page(s): 187 - 196
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (971 KB)  

    A yield model is developed to estimate yield values for the serial superchip. The superchip is a large silicon chip containing many processing elements together with a communication network. Owing to its large area, the superchip concept will not be economically viable if current silicon processing technology and conventional nonredundant VLSI design techniques are employed to implement it. This p... View full abstract»

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  • Design of SIMD microprocessor array

    Publication Year: 1989 , Page(s): 197 - 204
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (916 KB)  

    There are several important issues that must be considered in the design of highly parallel SIMD machines. Factors such as machine programmability, support for flexible interprocessor communications and a suitable I/O system all contribute to the design of a successful SIMD computer system. The microprocessor array ( mu PA) is an SIMD design study performed in conclusion to an Alvey funded project... View full abstract»

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  • Split-step algorithm for matrix preconditioning and inversion on systolic arrays

    Publication Year: 1989 , Page(s): 205 - 210
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (587 KB)  

    New algorithms for preconditioning and inversion of symmetric positive-definite matrices are proposed in this paper. These algorithms have a parallel structure and are suitable for realisation on systolic arrays. The algorithms are based on the repeated use of a polynomial preconditioning technique. Matrix-matrix multiplications constitute the major computations in these algorithms. On a systolic ... View full abstract»

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  • Impact of GaAs and Si technologies on adder characteristics

    Publication Year: 1989 , Page(s): 217 - 223
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (562 KB)  

    Two radiation-hard technologies, E/D-MESFET GaAs and SOS-CMOS Si are compared, from the point of view of propagation delay and VLSI layout area, for different types of adders. The major intention was to evaluate the impact of two technologies on the adder design. However, the overall results are more general. They show how the adder design trade-offs change when the dependency of gate delays on fa... View full abstract»

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