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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Displaying Results 1 - 24 of 24

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2015, Page(s): C2
| PDF (137 KB)
• ### Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits

Publication Year: 2015, Page(s):1381 - 1389
Cited by:  Papers (2)  |  Patents (1)
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Production of cost-effective secure integrated chips, such as smart cards, requires hardware designers to consider tradeoffs in size, security, and power consumption. To design successful security-centric designs, the low-level hardware must contain built-in protection mechanisms to supplement cryptographic algorithms, such as advanced encryption standard and triple data encryption standard by pre... View full abstract»

• ### Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Publication Year: 2015, Page(s):1390 - 1401
Cited by:  Papers (6)
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Near-threshold operation enables high energy efficiency, but requires proper design techniques to deal with performance loss and increased sensitivity to process variations. In this paper, we address both issues with two synergistic approaches. First, we introduce a novel body-biasing technique to mitigate the performance loss at near-threshold voltages while not requiring any additional circuitry... View full abstract»

• ### Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems

Publication Year: 2015, Page(s):1402 - 1414
Cited by:  Papers (2)
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Through energy harvesting system, new energy sources are made available immediately for many advanced applications based on environmentally embedded systems. However, the harvested power, such as the solar energy, varies significantly under different ambient conditions, which in turn affects the energy conversion efficiency. In this paper, we propose an approach for designing power-adaptive comput... View full abstract»

• ### High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost

Publication Year: 2015, Page(s):1415 - 1428
Cited by:  Papers (1)
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A gate array has a great advantage in that the extra cost required for customizing VLSI masks is low and the lead time needed to obtain an ASIC is short. Hence, it is widely and generally used in the ASIC industry as a major semicustomized VLSI design methodology. This paper presents high-density RAM/ROM macros using memory-oriented CMOS gate-array base cells. The metatile methodology along with a... View full abstract»

• ### A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation

Publication Year: 2015, Page(s):1429 - 1438
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In this paper, we present an efficient countermeasure against fault sensitivity analysis (FSA) based on configurable delay blocks (CDBs). FSA is a new type of fault attack, which exploits the relationship between fault sensitivity (FS) and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against differential fault an... View full abstract»

• ### Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores

Publication Year: 2015, Page(s):1439 - 1447
Cited by:  Papers (1)
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The increased use of multicore chips diminishes per-core complexity and also demands parallel design and test technologies. An especially important evolution of the multicore chip has been the use of multiple identical cores, providing a homogenous system with various merits. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores and identifying ... View full abstract»

• ### A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF $(2^{m})$

Publication Year: 2015, Page(s):1448 - 1458
Cited by:  Papers (1)
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This paper presents a novel low-complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF(2m). For an m input circuit, the proposed scheme can correct m ≤ Dw ≤ 3m/2 -1 multiple error combinations out of all the possible 2m - 1 errors, wh... View full abstract»

• ### Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels

Publication Year: 2015, Page(s):1459 - 1470
Cited by:  Papers (4)
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We present an approach for overcoming computational errors at run time that originate from static hardware faults in digital processors. The approach is based on embedded machine-learning stages that learn and model the statistics of the computational outputs in the presence of errors, resulting in an error-aware model for embedded analysis. We demonstrate, in hardware, two systems for analyzing s... View full abstract»

• ### A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification

Publication Year: 2015, Page(s):1471 - 1484
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This paper presents a parallel digital VLSI architecture for combined support vector machine (SVM) training and classification. For the first time, cascade SVM, a powerful training algorithm, is leveraged to significantly improve the scalability of hardware-based SVM training and develop an efficient parallel VLSI architecture. The presented architecture achieves excellent scalability by spreading... View full abstract»

• ### A Modular Shared L2 Memory Design for 3-D Integration

Publication Year: 2015, Page(s):1485 - 1498
Cited by:  Papers (2)
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Large required size, and tolerance to latency and variations in memory access time make L2 memory a suitable option for 3-D integration. In this paper, we present a synthesizable 3-D-stackable L2 memory IP component, which can be attached to a cluster-based multicore platform through its network-on-chip interfaces offering high-bandwidth memory access with low average latency. Our design implement... View full abstract»

• ### Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits

Publication Year: 2015, Page(s):1499 - 1507
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Bulk FinFETs have emerged as the solution to short-channel effects at the 22-nm technology node and beyond. The capability of 3-D stacking of dies from various technologies will eventually enable stacking FinFET dies within 3-D integrated circuits. Within 3-D circuits, through silicon vias (TSVs) are a known source of substrate noise in planar bulk technologies. While FinFETs are expected to demon... View full abstract»

• ### An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management

Publication Year: 2015, Page(s):1508 - 1517
Cited by:  Papers (1)
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We propose an all-digital on-chip time-domain temperature sensor for system-on-a-chip (SoC) thermal management. For on-chip purposes, the proposed temperature sensor achieves energy- and area-efficient and fast thermal monitoring by adopting a digitally controlled oscillator (DCO) with the frequency divider and XNOR gate to generate temperature-dependent pulse. The frequency divider with the fine ... View full abstract»

• ### Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product

Publication Year: 2015, Page(s):1518 - 1527
Cited by:  Papers (1)
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This paper discusses the ultralow-voltage (ULV) design strategy for high-speed flash analog-to-digital converters (ADCs). A lower supply voltage decreases the energy consumption at the cost of conversion speed. In this paper, a new index, the figure-of-merit (FoM)-delay (FD) product, is introduced to provide a balance between the energy efficiency and conversion speed. As a prototype, a 0.5 V, 420... View full abstract»

• ### An $80times$ Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18- $mu$ m CMOS

Publication Year: 2015, Page(s):1528 - 1533
Cited by:  Papers (1)
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An analog-implemented time-difference amplifier applied for coarse-fine time-to-digital converters is presented in this paper. Implemented in 0.18-μm CMOS process, a time difference within 225 ps can be amplified 80× linearly under maximum frequency of 25 MHz. Measured maximum gain error is 4.1%. Measured output rms jitter is 84.5 ps under gain of 80×. The time amplifier consu... View full abstract»

• ### Period Jitter of Frequency-Locked Loops

Publication Year: 2015, Page(s):1534 - 1546
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This paper presents a spectral analysis of period jitter of frequency-locked loops (FLLs). It is shown that the period jitter of the output clock of the FLL due to stationary noise sources is cyclostationary. It is further shown that the FLL behaves as a time variant loop and there is translation of jitter frequency at the output. These effects cannot be explained from the usual linear time invari... View full abstract»

• ### A Sub- ${boldsymbol kT}/boldsymbol q$ Voltage Reference Operating at 150 mV

Publication Year: 2015, Page(s):1547 - 1551
Cited by:  Papers (9)
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We propose a subthreshold CMOS voltage reference operating with a minimum supply voltage of only 150 mV, which is three times lower than the minimum value presently reported in the literature. The generated reference voltage is only 17.69 mV. This result has been achieved by introducing a temperature compensation technique that does not require the drain-source voltage of each MOSFET to be larger ... View full abstract»

• ### Optimization of Overdrive Signoff in High-Performance and Low-Power ICs

Publication Year: 2015, Page(s):1552 - 1556
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In modern system-on-chip implementations, multimode design is commonly used to achieve better circuit performance and power across voltage-scaled, “turbo” and other operating modes. To the best of our knowledge, there is no available systematic analysis or methodology for the selection of associated signoff modes for multimode circuit implementations. In this brief, we observe signif... View full abstract»

• ### A Fully Digital ASK Demodulator With Digital Calibration for Bioimplantable Devices

Publication Year: 2015, Page(s):1557 - 1561
Cited by:  Papers (1)
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A new fully digital high-efficiency ASK demodulator for detecting data via inductive link is proposed. The proposed demodulator does not use any passive component and is compatible with standard CMOS digital technology. The modulation index, modulation rate, and power consumption of the proposed structure are <;4%, 100%, and 118.2 μW, respectively, at the carrier frequency of 13.56 MHz. ... View full abstract»

Publication Year: 2015, Page(s):1562 - 1566
Cited by:  Papers (7)
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Advances in CMOS technology have made digital circuits and systems very sensitive to manufacturing variations, aging, and/or soft errors. Fault-tolerant techniques using hardware redundancy have been extensively investigated for improving reliability. Quadded logic (QL) is an interwoven redundant logic technique that corrects errors by switching them from critical to subcritical status; however, Q... View full abstract»

• ### Online Fault Tolerance Technique for TSV-Based 3-D-IC

Publication Year: 2015, Page(s):1567 - 1571
Cited by:  Papers (1)
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This brief presents the design, validation, and evaluation of an efficient online fault tolerance technique for fault detection and recovery in presence of three through-silicon-vias (TSV) defects: 1) voids; 2) delamination between TSV and landing pad; and 3) TSV short-to-substrate. The technique employs transition delay test for TSV fault detection. Fault recovery is achieved by employing redunda... View full abstract»

• ### A 1.2-V 450-μW $G_{m}$ - $C$ Bluetooth Channel Filter Using a Novel Gain-Boosted Tunable Transconductor

Publication Year: 2015, Page(s):1572 - 1576
Cited by:  Papers (2)
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A third-order Gm-C Chebyshev low-pass filter based on a novel gain-boosted tunable transconductor is presented. The transconductor employs local negative feedback for linearization controlling the drain voltage of the input transistors biased in the triode region. The gain boosted feedback amplifier is based on quasi-floating gate MOS transistors and its adjustable biasing current allow... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2015, Page(s): C3
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu