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# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 55

Publication Year: 2015, Page(s):C1 - 2370
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2015, Page(s): C2
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• ### Analysis of Effective Gate Length Modulation by X-Ray Irradiation for Fully Depleted SOI p-MOSFETs

Publication Year: 2015, Page(s):2371 - 2376
Cited by:  Papers (3)
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An X-ray irradiation degradation mechanism has been investigated for fully depleted-silicon-on-insulator (FD-SOI) p-channel MOSFETs (p-MOSFETs). It is found that the drain current degradation by the X-ray irradiation has gate length dependence showing 20% degradation for L = 0.2 μm, while 8% for L = 10 μm after the 1.4 kGy(Si) X-ray irradiation. Using Terada's method, it was found th... View full abstract»

• ### On the Performance of Lateral SiGe Heterojunction Bipolar Transistors With Partially Depleted Base

Publication Year: 2015, Page(s):2377 - 2383
Cited by:  Papers (2)
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This paper discusses improvements to a lateral bipolar device capable of integration into the existing CMOS process flow. With the help of simulations, we demonstrate that the emitter transit time limits the cutoff frequency of a lateral bipolar device. We show that with the introduction of a heterojunction and a partially depleted base, we can decrease the emitter transit time and increase the cu... View full abstract»

• ### Graded Applications of NQS Theory for Modeling Correlated Noise in SiGe HBTs

Publication Year: 2015, Page(s):2384 - 2389
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In this paper, we develop a correlated noise model for bipolar transistors from an accurate nonquasi-static model. The proposed noise model includes the signal delay through base-collector space-charge region and is implemented using four extra nodes. We also present a simplified version of the same model that requires only two extra nodes. A further simplified version that uses only one extra nod... View full abstract»

• ### Gate-Induced Source Tunneling FET (GISTFET)

Publication Year: 2015, Page(s):2390 - 2395
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We propose a device, the gate-induced source tunneling FET (GISTFET), that uses two gate work functions to modulate lateral tunneling. The performance of the device is largely independent of the details of the chemical doping profile, potentially freeing device design from issues related to solid solubility, junction abruptness, and dopant variability. We demonstrate the advantages of the device o... View full abstract»

• ### Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology

Publication Year: 2015, Page(s):2396 - 2403
Cited by:  Papers (3)
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We propose a novel standard ternary inverter (STI) based on nanoscale CMOS technology for a compact design of multivalued logic. Using the gate bias independent OFF-state mechanisms of junction band-to-band tunneling (BTBT), tristate STI operation has been demonstrated in the conventional binary CMOS inverter by TCAD device and mixed-mode circuit simulation with 32-nm high-κ/metal-gate tech... View full abstract»

• ### PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET

Publication Year: 2015, Page(s):2404 - 2409
Cited by:  Papers (10)
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This paper presents a new design of dopingless dynamically configurable double-gate tunnel FET (TFET) for process-voltage-temperature (PVT)-aware applications. The dopingless FETs have recently been explored and showed very good electrostatic control over the channel with reduced thermal budget and process complexity. The proposed device makes use of the dopingless concept, but instead of charge p... View full abstract»

• ### Investigation of Self-Heating Effects in a 10-nm SOI-MOSFET With an Insulator Region Using Electrothermal Modeling

Publication Year: 2015, Page(s):2410 - 2415
Cited by:  Papers (3)
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This paper investigates the heat transfer and temperature distribution as well as electric fields in a 10-nm MOSFET and insulator region silicon-on-insulator MOSFET (IR-SOI-MOSFET). An electrothermal model based on a dual-phase-lag model coupled with a second-order temperature-jump boundary condition and drift-diffusion (D-D) model has been elaborated. The D-D model is used to take into account th... View full abstract»

• ### Influence of Field-Plate Configuration on Power Dissipation and Temperature Profiles in AlGaN/GaN on Silicon HEMTs

Publication Year: 2015, Page(s):2416 - 2422
Cited by:  Papers (4)
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Thermal analysis of AlGaN/GaN high-electron mobility transistors on silicon has been performed with emphasis on the influence of the field-plate configuration on power dissipation and temperature profiles along a 2-D electron gas. The results highlight the importance of the field plates in power dissipation and show the difference between various field-plate configurations. Consequently, their des... View full abstract»

• ### Current Collapse Reduction in AlGaN/GaN HEMTs by High-Pressure Water Vapor Annealing

Publication Year: 2015, Page(s):2423 - 2428
Cited by:  Papers (7)
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We have demonstrated for the first time a remarkable reduction of current collapse in AlGaN/GaN high-electron-mobility transistors (HEMTs) by high-pressure water vapor annealing (HPWVA). The device subjected to HPWVA exhibited considerably low dynamic ON-resistance (RON), suggesting highly improved performance of these devices. Analyses of the results on normalized dynamic RON View full abstract»

• ### Field-Effect Mobility of InAs Surface Channel nMOSFET With Low $D_{rm it}$ Scaled Gate-Stack

Publication Year: 2015, Page(s):2429 - 2436
Cited by:  Papers (5)
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Frequency (100 Hz ≤ f ≤ 1 MHz) and temperature (-50 ≤ T 20 °C) characteristics of low interface state density Dit high-κ gate-stacks on n-InAs have been investigated. Capacitance-voltage (C-V) curves exhibit typical accumulation/depletion/inversion behavior with midgap Dit of 2 × 1011 and 4 × 1011 cm-... View full abstract»

• ### The Impact of Nongray Thermal Transport on the Temperature of AlGaN/GaN HFETs

Publication Year: 2015, Page(s):2437 - 2444
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The hotspot temperature in AlGaN/GaN heterostructure FETs has been of great interest due to its effect on the reliability of these devices. Both the nanoscale heat transfer effects and complex energy transfer mechanism from electrons to lattice are factors affecting the hotspot temperature, which is not accounted for in continuum level thermal simulations. The effects of heat generation zone size ... View full abstract»

• ### Quantum Transport in AlGaSb/InAs TFETs With Gate Field In-Line With Tunneling Direction

Publication Year: 2015, Page(s):2445 - 2449
Cited by:  Papers (1)
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Quantum transport simulations are performed in tunneling FETs (TFETs) with the gate electric field in-line with the tunneling junction direction (in-line TFETs). Charge self-consistency and thermalization effects are included in a semiclassical Poisson solution to compute the electrostatic potential. The obtained potential is then used for current calculation with the ballistic nonequilibrium Gree... View full abstract»

• ### Performance Evaluation of In0.53Ga0.47As Esaki Tunnel Diodes on Silicon and InP Substrates

Publication Year: 2015, Page(s):2450 - 2456
Cited by:  Papers (4)
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In0.53Ga0.47As Esaki tunnel diodes grown by molecular beam epitaxy on an Si substrate via a graded buffer and control In0.53Ga0.47As Esaki tunnel diodes grown on an InP substrate are compared in this paper. Statistics are used as a tool to show peak-to-valley ratio for the III-V on Si sample and the control that perform similarly below 8.6 × 10 View full abstract»

• ### Screening in Ultrashort (5 nm) Channel MoS2 Transistors: A Full-Band Quantum Transport Study

Publication Year: 2015, Page(s):2457 - 2463
Cited by:  Papers (6)
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Full-band ballistic quantum transport calculations were used to study the screening effects in ultrashort-channel few-layer MoS2 transistors. A large density of states resulted in small screening lengths while inhibiting direct source-to-drain tunneling. Short-channel effects were observed even for the structurally confined 2-D transistors resulting in degraded electrostatic control. El... View full abstract»

• ### Interface State Artefact in Long Gate-Length AlGaN/GaN HEMTs

Publication Year: 2015, Page(s):2464 - 2469
Cited by:  Papers (2)
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Dispersion in capacitance and conductance measurements in AlGaN/GaN high-electron mobility transistors is typically interpreted as resulting from interface states. Measurements on varying gate-length devices and a model of an interface-trap-free device are used to demonstrate that the distributed-resistance-induced dispersion is significant for 1-MHz measurements if the gate length exceeds ~10 &#x... View full abstract»

• ### Charge Transport in Magnetic Semiconductor p-n Heterojunctions

Publication Year: 2015, Page(s):2470 - 2474
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Previously, the p-n-p bipolar magnetic junction transistor was demonstrated using a magnetic semiconductor InMnAs as the collector. A current gain βdc as high as 20 of the transistor is observed at 300 K. A negative magnetoamplification of -150% is obtained when the applied magnetic field is 8 T. In order to assess the gain mechanism for such transistors, we measured the minority... View full abstract»

• ### Temperature Dependence of the Surface- and Buffer-Induced Current Collapse in GaN High-Electron Mobility Transistors on Si Substrate

Publication Year: 2015, Page(s):2475 - 2480
Cited by:  Papers (5)
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The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature depen... View full abstract»

• ### GaN-Based Enhancement-Mode Metal–Oxide–Semiconductor High-Electron Mobility Transistors Using LiNbO3 Ferroelectric Insulator on Gate-Recessed Structure

Publication Year: 2015, Page(s):2481 - 2487
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To fabricate AlGaN/gallium nitride (GaN) enhancement-mode metal-oxide-semiconductor high-electron mobility transistors (E-MOSHEMTs), the gate-recessed structure and the LiNbO3 ferroelectric film were utilized in this paper. The LiNbO3 ferroelectric films deposited on the photoelectrochemically etched gate-recessed regions of the AlGaN/GaN E-MOSHEMTs as the gate insulator usin... View full abstract»

• ### A Novel Approach Using Discrete Grain-Boundary Traps to Study the Variability of 3-D Vertical-Gate NAND Flash Memory Cells

Publication Year: 2015, Page(s):2488 - 2493
Cited by:  Papers (1)
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The 3-D NAND flash memory architectures will be a future trend, because they provide high memory capacity without aggressively scaling down. A vertical-gate (VG) structure composed of polysilicon (poly-Si) channels is a promising 3-D structure that could facilitate realizing an extremely tight-pitch NAND flash memory cell with high memory capacity. However, the variability of the VG memory cell in... View full abstract»

• ### HfO2-Based OxRAM Devices as Synapses for Convolutional Neural Networks

Publication Year: 2015, Page(s):2494 - 2501
Cited by:  Papers (22)
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In this paper, the use of HfO2-based oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in a convolutional neural network (CNN) is studied. We employed an artificial synapse composed of multiple OxRAM cells connected in parallel, thereby providing synaptic efficacies. Electrical characterization results show that the proposed HfO2-based... View full abstract»

• ### Impact of Intercell and Intracell Variability on Forming and Switching Parameters in RRAM Arrays

Publication Year: 2015, Page(s):2502 - 2509
Cited by:  Papers (12)
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The intercell variability of the initial state and the impact of dc and pulse forming on intercell variability as well as on intracell variability in TiN/HfO2/Ti/TiN 1 transistor - 1 resistor (1T-1R) devices in 4-kb memory arrays were investigated. Nearly 78% of devices on particular arrays were dc formed with a wordline (WL) voltage VWL = 1.4 V and a bitline (BL) voltage V View full abstract»

• ### Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example

Publication Year: 2015, Page(s):2510 - 2516
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This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The ... View full abstract»

• ### Multitime Programmable Memory Cell With Improved MOS Capacitor in Standard CMOS Process

Publication Year: 2015, Page(s):2517 - 2523
Cited by:  Papers (3)
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A multitime programmable memory cell with improved MOS capacitor is proposed in this paper. The improved MOS capacitor has p-type junction near the channel, which prevents the capacitor from deep depletion, and this helps to improve the cell's program/erase efficiency and stability. A test chip is fabricated using a 0.13-μm standard CMOS process without any extra masks or process modificati... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy