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IEE Proceedings - Computers and Digital Techniques

Issue 3 • Date May 1994

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Displaying Results 1 - 8 of 8
  • Automated technique for high-level circuit synthesis from temporal logic specifications

    Publication Year: 1994, Page(s):145 - 152
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (556 KB)

    A general-purpose strategy for the synthesis of digital circuits from high-level behavioural specifications expressed in the temporal-logic language Tempura is described. This strategy has been implemented as a synthesis tool called AST, and the application of AST to part of the specification for an error-encoder circuit is examined View full abstract»

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  • Processor allocation strategies for modified hypercubes

    Publication Year: 1994, Page(s):196 - 204
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (636 KB)

    Modified hypercubes (MHs) have been proposed as building blocks for hypercube-based parallel systems that support the application of incremental growth techniques. In contrast, implementing the standard hypercube cannot be expanded in practice. However, processor allocation for MHs is a more difficult task due to a slight deviation in their topology from that of the standard hypercube. The paper p... View full abstract»

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  • Dual forms of Reed-Muller expansions

    Publication Year: 1994, Page(s):184 - 192
    Cited by:  Papers (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (480 KB)

    The dual forms of Reed-Muller expansions based on the operations of logical equivalence and OR are investigated. The transforms describing the various fixed and mixed polarity product-of-sums expressions are derived and shown to be easily related to their counterparts for the normal sum-of-products forms. It is demonstrated that if the synthesis is restricted to using only the consistent fixed or ... View full abstract»

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  • Effect of nonuniform traffic on the performance of multistage interconnection networks

    Publication Year: 1994, Page(s):169 - 176
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (524 KB)

    Multistage interconnection networks are used to connect processors to memories in shared memory multiprocessor systems. The performance evaluation of such networks is usually based on the assumption of a uniform memory reference pattern. Hot spots in such networks give rise to a nonuniform memory reference pattern and result in a degradation in performance. A comparison of the performance of unbuf... View full abstract»

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  • Design for testability of sequential circuits

    Publication Year: 1994, Page(s):153 - 160
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (496 KB)

    The paper presents a new approach for design-for-testability (DFT) of sequential circuits. The proposed approach is based on augmenting the system under test (SUT) which is modelled as a Mealy machine, with circuitry such that the combinational part of the SUT and the sequential part (i.e. The flip-flops can be tested independently (disjoint testing). A partial parallel scan method is used with a ... View full abstract»

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  • Public-key cryptosystem design based on factoring and discrete logarithms

    Publication Year: 1994, Page(s):193 - 195
    Cited by:  Papers (10)  |  Patents (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (228 KB)

    Most existing cryptosystem designs incorporate just one cryptographic assumption, such as factoring or discrete logarithms. These assumptions appear secure today; but, it is possible that efficient algorithms will be developed in the future to break one or more of these assumptions. It is very unlikely that multiple cryptographic assumptions would simultaneously become easy to solve. Enhancing sec... View full abstract»

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  • Application of the CMAC input encoding scheme in the N-tuple approximation network

    Publication Year: 1994, Page(s):177 - 183
    Cited by:  Papers (7)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (556 KB)

    The N-tuple approximation network offers many advantages over conventional neural networks in terms of speed of operation and its ability to realise arbitrary nonlinear mappings. However, its generalisation/selectivity properties depend strongly on the form of input encoding being used in the system. The paper analyses the suitability of use of the CMAC code for the N-tuple networks, and compares ... View full abstract»

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  • Unified approach to designing parallel Winograd algorithms

    Publication Year: 1994, Page(s):161 - 168
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (348 KB)

    Although the recurrence equation for the Winograd algorithm is uniform, no unified approach has been proposed to design parallel Winograd algorithms. The authors propose a unified approach to designing parallel Winograd algorithms. Using this approach, several parallel algorithms are designed. These algorithms are executed on regular arrays including conventional systolic arrays and nonplanar regu... View full abstract»

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